Decision Tree Node Ordering for Memory Access Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing decision tree inference methods, such as random forest and gradient boosting, are resource-intensive and time-consuming due to the sequential processing of binary decision trees, which can be accelerated by optimizing the memory access and ordering of nodes based on their likelihood of access.

Innovation Solution

A method that reorders decision tree nodes according to their likelihood of access and maps them onto contiguous memory blocks using a depth-first search order, allowing for efficient execution of node attributes stored in memory blocks, thereby reducing memory access and improving cache performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If decision tree nodes are processed sequentially using existing methods, then the inference process is simple to implement, but the inference time is long and resource consumption is high

Engineering Contradiction:
Improveinference speedVSAvoidinference time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-ordering the nodes in the decision tree according to their likelihood of access before inference begins. During the inference process, nodes are arranged in the memory buffer in this predetermined order, so that when inference executes, the processor can access nodes in an optimal sequence without needing to determine access patterns dynamically during execution. This pre-arrangement significantly reduces inference time while maintaining implementation simplicity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If nodes are mapped onto memory blocks without optimization, then the memory structure is simple, but memory access efficiency is low and cache performance is poor

Engineering Contradiction:
Improvememory access efficiencyVSAvoidmemory mapping complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by mapping nodes onto contiguous memory blocks according to their local access patterns. Specifically, nodes that are more likely to be accessed together or in sequence are placed in adjacent memory blocks. This local optimization of memory arrangement ensures that when the processor accesses one node, nearby nodes that are likely to be accessed next are already in adjacent memory locations, improving cache utilization and memory access efficiency without requiring complex global memory management.

Inventive Principle:
Principle #3Local quality

3Productivity

If child nodes are not ordered by likelihood of access, then the tree structure is straightforward, but the probability of accessing less likely child nodes inefficiently increases

Engineering Contradiction:
Improvenode access efficiencyVSAvoidnode ordering complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by ordering child nodes based on the parameter of access likelihood probability. During the tree construction or preprocessing phase, each child node is assigned an order based on how likely it is to be accessed given its parent node. This parameter-based ordering transforms the traditional unoptimized child node arrangement into an access-optimized sequence, ensuring that the processor encounters nodes in the most probable access order, thereby maximizing efficiency without adding significant structural complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11886725B2Accelerating decision tree inferences
Publication Date: 2024.01.30 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11886725B2 patent drawing
  • US11886725B2 patent drawing
  • US11886725B2 patent drawing

AI summary

Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.