Deck-Based Erase Sequencing for Lower-Latency HGB Writes
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Solution Overview
Problem
Memory systems with half good blocks (HGBs) experience higher latency due to the need to complete erasing and writing operations on both upper and lower HGBs before starting new write operations, leading to inefficient use of resources and increased latency.
Innovation Solution
Implementing a deck-based erase function where erase and write operations are performed in alternating stages, specifically erasing and writing to upper HGBs before addressing lower HGBs, allowing for reduced latency by optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase and write operations are performed sequentially on all blocks before starting new write operations, then data integrity is maintained, but latency increases and resource utilization becomes inefficient
Solution Approach 1:
The patent segments the erase and write operations into alternating stages across different block sets. Instead of completing all erase operations before write operations, the system divides blocks into multiple sets and performs erase operations on one set while simultaneously performing write operations on another set, thereby overlapping these operations in time and reducing total latency
Solution Approach 2:
The patent implements continuous useful action by ensuring that while one set of blocks is being erased, another set is being written to. This overlapping of operations eliminates idle time and maintains continuous productive work, improving resource utilization and reducing overall latency while preserving data integrity through proper staging
2Productivity
If all erase operations are completed before write operations begin, then resource conflicts are avoided, but productivity decreases due to idle time
Solution Approach 1:
The patent segments blocks into multiple sets (e.g., first set, second set, third set) and assigns different operation stages to each set. This segmentation allows the system to manage multiple operation streams simultaneously, improving productivity by eliminating idle time while controlling complexity through structured organization of block sets and their associated operations
Solution Approach 2:
The patent applies preliminary action by preparing and organizing blocks into different sets in advance, with each set designated for specific operation stages. This pre-organization enables smooth transitions between erase and write operations without conflicts, improving resource utilization while maintaining manageable system complexity through predetermined operation sequences
Data Source
AI summary
Methods, systems, and devices for a deck-based erase function are described. A memory system may perform alternating erase operations and write operations on a virtual block configured with blocks constructed from half good blocks (HGBs). For example, the memory system may erase and subsequently write data to a first subset of HGBs associated with one or more memory dies of the memory system, before erasing and subsequently writing data to a second subset of HGBs associated with the one or more memory dies. In some cases, the memory system may determine the first subset of HGBs has been filled by the write operations, prior to erasing the second subset of HGBs. In other cases, the memory system may identify an idle time during writing to the first subset of HGBs, and begin erasing the second subset of HGBs during the idle time.