Deck-Level Shunting Circuitry for 3D Memory Scaling
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Solution Overview
Problem
As memory devices scale with increasing layers or decks above a substrate, the area required for substrate-based circuitry increases, leading to scaling limitations due to the limited substrate area that must support growing quantities of decks and associated circuitry.
Innovation Solution
Implementing deck selection and shunting circuitry, such as deck selection transistors and shunting transistors, distributed among the decks to leverage common substrate-based circuitry, allowing for shared logic or addressing signals and reducing the need for extensive substrate-based circuitry by moving decoding or addressing into decks above the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If substrate-based circuitry is used to support memory decks, then circuit functionality is achieved, but substrate area increases limiting scaling
Solution Approach 1:
The patent moves circuitry from the substrate plane to the vertical dimension by implementing deck selection and shunting circuitry distributed among decks above the substrate. This transitions the architecture from two-dimensional substrate-based circuitry to three-dimensional distributed circuitry, allowing memory scaling without proportional increases in substrate area.
Solution Approach 2:
The patent segments the circuitry by distributing deck selection and shunting circuitry across multiple decks rather than consolidating it on the substrate. Each deck contains its own circuitry, allowing independent operation and reducing the burden on substrate area while maintaining full circuit functionality.
2Quantity of substance
If more decks are added to increase memory capacity, then storage capacity improves, but substrate area requirements increase
Solution Approach 1:
The patent enables increased memory capacity by adding decks in the vertical dimension rather than expanding substrate area horizontally. Each additional deck contributes to storage capacity while the distributed circuitry architecture ensures that substrate area does not increase proportionally with the number of decks.
Solution Approach 2:
The patent implements shared logic and addressing signals that can serve multiple decks simultaneously. This multi-functionality allows the same substrate-based circuitry to support an increasing number of decks, enabling memory capacity to scale without linear increases in substrate area.
3Area of stationary object
If deck selection and shunting circuitry are distributed among decks, then substrate area is reduced, but circuit complexity increases
Solution Approach 1:
The patent segments circuitry into modular deck-level units with standardized functions. Each deck contains similar circuitry elements (selection transistors, shunting transistors), which reduces the overall complexity by creating repeatable patterns rather than requiring unique complex circuit designs for each deck.
Solution Approach 2:
The patent merges deck selection and shunting functions into a unified distributed architecture where both functions are implemented at the deck level using similar transistor structures. This consolidation of functions into a standardized framework reduces complexity compared to having separate dedicated circuits for each function.
Data Source
AI summary
Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.