3D NAND Deck Reset Read for Data Retention
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Solution Overview
Problem
The 3D NAND architecture in storage devices leads to charge accumulation in vertical pillars, causing shallowly trapped electrons to detrap and result in a significant threshold voltage downshift, negatively impacting data retention and increasing the risk of stable state read disturb, which can lead to data loss.
Innovation Solution
A deck reset read mechanism is implemented, allowing for selective biasing of different decks in a 3D NAND storage array to balance data retention with the risk of stable state read disturb by injecting holes into pillars and managing the accumulation of electron and hole carriers, using a combination of weak erase pulses and deck reset read pulses to maintain holes in selected decks and introduce electrons into unselected decks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If holes are introduced into the pillar to facilitate detrapping of shallowly trapped electrons, then data retention is improved, but stable state read disturb increases due to hot carrier injection
Solution Approach 1:
The storage device is divided into multiple decks, allowing different voltage biases to be applied to different decks. This segmentation enables selective management of charge carriers in different spatial regions, resolving the contradiction by isolating the harmful effects to specific decks while maintaining benefits in others.
Solution Approach 2:
Different voltage biases are applied to different decks based on local conditions. Decks experiencing significant threshold voltage downshift are subjected to hole injection (high bias), while decks in stable state maintain low bias to prevent hot carrier injection. This local differentiation resolves the contradiction by applying the appropriate treatment to each deck's specific state.
2Productivity
If electrons are introduced into the pillar through charging wordlines, then array operations are facilitated, but threshold voltage downshift increases due to detrap of shallowly trapped electrons
Solution Approach 1:
A deck reset read operation is performed before normal array operations to preemptively manage charge carrier states. This preliminary action introduces holes into pillars of decks that have accumulated excessive electrons, preventing subsequent threshold voltage downshift during normal operations while maintaining operational capability.
Solution Approach 2:
The deck reset read operation is periodically executed based on read count thresholds or time intervals. This periodic maintenance operation prevents accumulation of harmful charge carriers while allowing normal array operations to proceed between resets, resolving the contradiction between operational productivity and voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data retention while minimizing the risk of hot carrier injection disturb, allowing for flexible assignment of decks based on NAND characteristics, workload, and system policies, thereby maintaining data integrity and reducing the risk of data loss.
Implementation Method 1
Charging the wordlines creates an electric field in the pillar, which can boost the pillar, driving electron carriers into the pillar
Implementation Method 2
populating the pillars with holes can induce negative impacts, most notably stable state read disturb (SRD), characterized by hot carrier injection
Data Source
AI summary
A storage device includes a storage array having multiple decks of NAND cells in a three dimensional (3D) stack. There can be any number of decks that have multiple wordlines in vertical stacks. The decks include a first deck and a second deck. Bias circuitry can apply different voltages to different decks of the storage array. The bias circuitry can apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.