Decoded 2N-Bit Bitcells for Low-Latency Memory Access
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Solution Overview
Problem
The existing memory systems face increased read latency due to the need for decoder logic to convert encoded words into decoded words, which is critical in digital circuits where the read path is often the bottleneck for memory access.
Innovation Solution
The implementation of decoded 2n-bit bitcells that store a 2n-bit decoded word using 2n state nodes, eliminating the need for decoder logic in the read path by leveraging the 'one-hot' property of decoded words to retain and update bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If encoded words are stored in memory to minimize storage elements and circuit area, then area is reduced, but decoder logic is required in the read path which increases read latency
Solution Approach 1:
Instead of storing encoded words and decoding them during read operations, the invention inverts the approach by storing decoded words directly in memory. This eliminates the need for decoder logic in the read path, thereby reducing read latency while maintaining area efficiency through the use of one-hot encoded storage during write operations
2Loss of time
If decoded words are stored directly in memory to eliminate decoder logic and reduce read latency, then read latency is reduced, but more storage elements are required increasing circuit area
Solution Approach 1:
The invention uses dynamic encoding schemes where the memory stores decoded words in a one-hot encoded format during write operations. This dynamic approach allows the memory to maintain decoded word format for fast reading while using efficient encoding during writing, thus achieving both low read latency and area efficiency
Solution Approach 2:
The invention changes the parameter representation by storing decoded words with one-hot encoding properties. Each decoded word is represented such that only one bit is active (hot) at any given time, which allows for more efficient storage utilization and reduces the effective area required while maintaining the ability to quickly access decoded data
Data Source
AI summary
Decoded 2n-bit bitcells in memory for storing decoded bits, and related systems and methods are disclosed. In one embodiment, a decoded 2n-bit bitcell containing 2n state nodes is provided. Each state node includes storage node to store decoded bit. Storage node provides bit to read bitline, coupled to decoded word output. Each state node includes active decoded bit input coupled to storage node that receives decoded bit from decoded word to store in storage node in response to write wordline. State node comprised of 2n−1 passive decoded bit inputs, each coupled to one of 2n−1 remaining storage nodes. 2n−1 passive decoded bit inputs receive 2n−1 decoded bits not received by active decoded bit input. State node includes logic that receives 2n−1 decoded bits. Logic retains decoded bit, provides it to passive decoded bit output. Passive decoded word output is coupled to storage node to store decoded bit in storage node.