Decoded Instruction Cache Merge Logic for Reducing Redundant Storage

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Solution Overview

Problem

In data processing systems, the number of instruction decoders often falls short of the number of execution units, leading to inefficiencies in decoding instructions due to power, performance, and area constraints, and existing decoded instruction caches do not effectively utilize cache space when different paths through a fetch granule result in redundant storage and re-decoding of instructions.

Innovation Solution

The implementation of a decoded instruction cache with allocation circuitry that detects merge conditions between different paths through a fetch granule, allowing for the updating of existing cache blocks to store both initial and additional decoded instructions, thereby reducing redundant storage and re-decoding by merging newly decoded instructions into existing cache blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of instruction decoders is increased to match the number of execution units, then the decoding performance is improved, but the power consumption and area increase

Engineering Contradiction:
Improvedecoding performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

Instructions are decoded in advance and stored in a decoded instruction cache before being needed by execution units. The allocation circuitry pre-allocates cache blocks for fetch granules, and merge detection circuitry detects when different paths through the same fetch granule are taken, merging the decoded instructions into the same cache block to avoid redundant decoding.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If a decoded instruction cache is used to store decoded instructions, then the decoding performance is improved, but the cache space is wasted when different paths through a fetch granule result in redundant storage

Engineering Contradiction:
Improvedecoding performanceVSAvoidcache space wastage
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

Merge detection circuitry monitors the instruction flow and detects when different paths through the same fetch granule are taken. When a merge condition is detected, the allocation circuitry updates the previously allocated cache block to include the newly decoded instructions from the different path, ensuring that cache space is efficiently utilized and redundant storage is avoided.

Inventive Principle:
Principle #23Feedback

3Productivity

If instructions are fetched and decoded for each execution cycle, then the execution performance is improved, but the time required for decoding increases

Engineering Contradiction:
Improveexecution performanceVSAvoiddecoding time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Instructions are decoded in advance and stored in a decoded instruction cache before being needed by execution units. This eliminates the need for real-time decoding during execution cycles, significantly reducing decoding time and allowing execution units to operate at full performance.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If the number of execution units is increased to execute N instructions per clock cycle, then the overall system performance is improved, but the decoding bottleneck becomes more severe

Engineering Contradiction:
Improvesystem performanceVSAvoiddecoder complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A decoded instruction cache acts as an intermediary between the fetch/decode stage and the execution units. The cache stores decoded instructions from multiple fetch granules and provides them to execution units on demand, decoupling the decoding rate from the execution rate and allowing multiple execution units to be served by a smaller number of decoders.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11042379B2Apparatus and method for providing decoded instructions from a decoded instruction cache
Publication Date: 2021.06.22 ARM LTD
  • US11042379B2 patent drawing
  • US11042379B2 patent drawing
  • US11042379B2 patent drawing

AI summary

A decoding apparatus has fetch circuitry, decode circuitry, and a decoded instruction cache. The decoded instruction cache comprises a plurality of cache blocks, where each cache block is arranged to store up to P decoded instructions from at least one fetch granule allocated to that cache block. When the corresponding decoded instruction for a required instruction is already stored in the decoded instruction cache, the decoded instruction is output in the stream of decoded instructions. Allocation circuitry is arranged, when a cache block is already allocated for existing decoded instructions from a particular fetch granule, and then additional decoded instructions from that particular fetch granule are subsequently produced by the decode circuitry due to a different path being taken through the fetch granule, to update the already allocated cache block to provide both the existing decoded instructions and the additional decoded instructions.