Iterative Decoder BER Testing Using Trapping Set Biasing

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Solution Overview

Problem

Conventional bit error rate testing methods are time-consuming and costly, requiring multiple cycles of data transmission to achieve low error rates, especially in high-volume production settings, due to the random nature of error events and the need for exhaustive testing of error control codes.

Innovation Solution

A bit error rate test system that uses a programmable transmitter to send biased bits corresponding to a trapping set of a code, measuring error events and calculating a true bit error rate through importance sampling and noise addition, allowing for rapid determination of low error rate behavior in devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional bit error rate testing methods are used with multiple cycles of data transmission, then measurement precision of low error rates is improved, but loss of time increases significantly

Engineering Contradiction:
Improvebit error rate measurement precisionVSAvoidtesting time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent pre-identifies trapping sets (error-prone bit patterns) before actual BER testing. By knowing which bit patterns are likely to cause errors, the system can directly inject these patterns into the test data, eliminating the need for multiple random transmission cycles to naturally encounter these error conditions. This preliminary identification and preparation of test cases dramatically reduces testing time while maintaining measurement precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter of test data from random bits to specifically biased bits that correspond to identified trapping sets. This parameter change transforms the testing approach from passive observation of random errors to active induction of known error patterns, enabling rapid and precise BER measurement without requiring extensive transmission cycles.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If exhaustive testing of error control codes is performed to ensure low bit error rates, then reliability of error protection is improved, but productivity decreases due to extended testing duration

Engineering Contradiction:
Improveerror protection reliabilityVSAvoidtesting throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and isolates the critical error-inducing patterns (trapping sets) from the vast space of all possible bit patterns. Instead of exhaustively testing all possible inputs, the system identifies and extracts only those specific patterns that are most likely to expose decoder vulnerabilities. This extraction approach maintains reliability by focusing on the most critical test cases while dramatically improving productivity by reducing the overall test volume.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by testing only the most critical trapping sets rather than all possible error patterns. By identifying a representative subset of trapping sets that capture the essential decoder vulnerabilities, the system achieves sufficient reliability for quality assurance without the prohibitive time cost of exhaustive testing, thus balancing reliability and productivity.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If multiple cycles of 1E12 bit streams are transmitted to guarantee low bit error rate, then measurement precision is improved, but loss of time increases substantially

Engineering Contradiction:
Improvebit error rate verification accuracyVSAvoidtransmission testing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent introduces trapping set identification as an intermediary step between test data generation and BER measurement. This intermediary process analyzes the error control code structure to identify vulnerable patterns, which then serve as the basis for constructing targeted test data. This intermediary analysis enables the system to achieve measurement precision equivalent to multiple transmission cycles but in a single pass, eliminating the time penalty of repeated transmissions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7739558B1Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing
Publication Date: 2010.06.15 MARVELL ASIA PTE LTD
  • US7739558B1 patent drawing
  • US7739558B1 patent drawing
  • US7739558B1 patent drawing

AI summary

A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.