Video Hardware Decoder Bit Stream Parsing Error Detection
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Solution Overview
Problem
Existing video hardware decoders lack effective mechanisms for detecting and processing errors in video streams, leading to decoding errors, crashes, and poor image quality due to complex and inflexible error detection logic, which is not suitable for hardware implementation and results in slow response times.
Innovation Solution
A control method and system for bit stream parsing error detection in video hardware decoders that perform bit stream security range detection, extremum detection, and anomaly detection, enabling exception handling and frame resets to enhance error detection sensitivity and robustness, allowing for timely error processing and improved image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex error detection and processing mechanisms are added to hardware video decoders, then error detection capability is improved, but device complexity and hardware resources increase significantly
Solution Approach 1:
The error detection mechanism is segmented into three independent modules: bit stream security range detection module, extremum detection module, and anomaly detection module. Each module independently detects specific types of errors through dedicated circuits, avoiding the need for a single complex error detection system. This segmentation allows parallel error detection across different layers (bit stream, syntax element, and decoding process) without significantly increasing overall hardware complexity.
Solution Approach 2:
The patent implements preliminary error detection by checking bit stream security ranges and extremum values before full decoding processing. The bit stream security range detection module validates syntax element values against predefined ranges early in the decoding process, and the extremum detection module checks for abnormal values before they propagate through the decoding pipeline. This preliminary action prevents erroneous data from consuming additional hardware resources during subsequent decoding stages.
2Reliability
If frame level error detection is implemented, then error detection coverage is improved, but detection flexibility is reduced and slice level errors cannot be handled
Solution Approach 1:
The error detection system is divided into three hierarchical levels: bit stream security range detection (syntax element level), extremum detection (macroblock/slice level), and anomaly detection (frame level). This segmentation enables the system to detect and handle errors at appropriate granularity - slice level errors are caught by the extremum detection module while frame level errors are caught by the anomaly detection module, providing both comprehensive coverage and flexible response.
Solution Approach 2:
The patent adds a new dimension to error detection by introducing multi-level hierarchical detection beyond traditional frame level. The bit stream security range detection operates at the syntax element dimension, extremum detection at the macroblock/slice dimension, and anomaly detection at the frame dimension. This multi-dimensional approach allows the system to detect errors at multiple granularities simultaneously, enhancing both coverage and flexibility.
3Reliability
If error detection processing is added to hardware decoders, then error detection capability is improved, but decoding performance is reduced
Solution Approach 1:
The bit stream security range detection and extremum detection modules perform preliminary error checking on syntax elements before they enter the main decoding pipeline. By validating ranges and detecting extremum values early, erroneous data is identified and handled before consuming significant decoding resources, minimizing impact on overall decoding performance.
Solution Approach 2:
The error detection and handling logic is extracted from the main decoding pipeline into separate dedicated modules. The bit stream security range detection module, extremum detection module, and anomaly detection module operate independently from the core video decoding operations. This extraction allows error detection to occur in parallel or as lightweight preprocessing, preventing error handling logic from becoming a bottleneck in the decoding performance path.
Data Source
AI summary
A control method/system for bit stream parsing error detection in a video hardware decoder including performing a bit stream security range detection on the obtained video stream to obtain a first detection result, performing a bit stream extremum detection on the obtained video stream to obtain a second detection result, an performing an anomaly detection on the process of bit stream parsing on the video stream, and performing an exception handling or a frame reset on the video stream according to the results of the anomaly detection based on the first detection result and the second detection result.