Address Decoder Circuitry for Bootloader-Safe Firmware Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current System on a Chip (SoC) systems require separate ROM and NVM memories, leading to increased costs and complexity, especially during software updates, as the bootloader is non-erasable and separate from the firmware, making it difficult to perform mass erasures without risking the bootloader's integrity.
Innovation Solution
An address decoder unit with an address selection circuitry that allows for a configurable separation between the bootloader and firmware sections, enabling a single mass erase command for the firmware section while keeping the bootloader intact, by selecting multiple memory cells or lines simultaneously based on a memory address input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate ROM and NVM memories are used for bootloader and firmware, then the bootloader can be kept non-erasable and protected, but the system complexity and cost increase
Solution Approach 1:
The patent merges the bootloader and firmware into a single NVM memory structure with configurable address space separation. The memory is divided into a first address space for bootloader and a second address space for firmware, both within the same NVM device. This eliminates the need for separate ROM and NVM components while maintaining bootloader protection through the decoder's address space configuration.
Solution Approach 2:
The NVM memory device serves multiple functions: it stores both the non-erasable bootloader and the erasable firmware, and can be selectively erased based on address space. The address decoder unit provides multi-functionality by enabling both protection of the bootloader area and selective erasure of the firmware area through a single memory device.
2Productivity
If a mass erase command is used to erase the firmware section, then the update time is reduced, but there is a risk of corrupting the bootloader
Solution Approach 1:
The memory address space is segmented into distinct first and second address spaces, with the first dedicated to bootloader and the second to firmware. The address decoder unit is configured to respond to erase commands by selectively erasing only the second address space (firmware) while leaving the first address space (bootloader) intact. This segmentation enables fast mass erasure of firmware without risking bootloader corruption.
Solution Approach 2:
The address decoder unit acts as an intermediary between the erase command and the memory cells. It intercepts the erase command, decodes the address information, and selectively activates erasure only for the firmware address space. This intermediary function protects the bootloader from unintended erasure while enabling rapid firmware updates.
3Device complexity
If the bootloader size is fixed in ROM, then the system structure is simple, but memory space is wasted when application needs change
Solution Approach 1:
The bootloader size and address space boundaries are made dynamic and configurable rather than fixed. The address decoder unit can be configured with different address space boundaries to accommodate varying bootloader sizes based on application requirements. This dynamic configuration allows optimal memory utilization without increasing physical device complexity.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
In one aspect the present disclosure relates to an address decoder unit (30) for a memory cell array (10), the address decoder unit (30) comprising: - an address decoder (31) comprising an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33), - an address selection circuitry (32) connected to the address decoder (31) and comprising a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array (10) and each of which corresponding to one memory address, - wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or below a memory address provided at the address input (33) and is further operable to unselect all address selection outputs (44, 45, 46) of an address space below or above, respectively, the memory address provided at the address input (33).