Decoder Circuit Size Reduction Using Matrix and Tournament Decoding
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Solution Overview
Problem
Existing liquid crystal display devices face challenges in reducing the size of the decoder circuit due to increased gradation requirements, with prior technologies focusing on reducing the number of gradation wires and intermediate voltage outputs but not adequately addressing the circuit size reduction for selecting multiple voltage values.
Innovation Solution
A display device with a decoder circuit that includes predecoder circuits, a selection circuit, and an intermediate voltage output circuit, utilizing matrix and tournament type decoder circuits to output voltages corresponding to 8-bit digital data, thereby reducing the overall circuit size by selecting and averaging voltages from multiple bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of gradation wires is reduced by using intermediate voltage outputs, then the overall circuit size is reduced, but the circuit size of the decoder portion that selects multiple voltage values is not sufficiently reduced
Solution Approach 1:
The decoder circuit is divided into multiple functional sections: a first decoder section that generates multiple voltage values, a second decoder section that selects two voltages from three candidates, and a third decoder section that handles edge cases. This segmentation allows each section to be optimized independently, reducing the overall complexity while maintaining the ability to output intermediate voltages for gradation control
Solution Approach 2:
The invention uses a tournament-type decoder structure where not all possible voltage combinations are fully explored. Instead, the circuit selectively evaluates only the necessary voltage pairs (out of potentially many combinations) to achieve the required gradation levels, reducing the decoder portion size while still providing sufficient voltage outputs for display control
2Area of stationary object
If the number of gradation wires is reduced, then the area occupied by chips is reduced, but the decoder circuit size increases due to increased number of gradations
Solution Approach 1:
The invention transitions from a traditional one-to-one mapping between digital input bits and voltage output wires to a many-to-one mapping where multiple voltage values are generated and then selectively combined. By introducing an intermediate selection dimension, the circuit can represent more gradation levels with fewer physical wires, reducing chip area while maintaining display quality
Data Source
AI summary
An object of the invention is to reduce the size of a decoder circuit of a display device. A decoder circuit which outputs voltages corresponding to 8-bit digital values includes a predecoder section, which includes an A decoder, B decoder, and C decoder, each of which is configured of a matrix type decoder circuit which carries out a three bits' worth of decoding, and a tournament type decoder circuit which carries out a three bits' worth of decoding, a selection circuit which, having input thereinto three voltages output respectively from the A decoder, B decoder, and C decoder, and applied to three output signal lines, selects two voltages of the three input voltages using a bit with one of the digital values and applies them to two output signal lines, and an intermediate voltage output circuit which, having input thereinto the two voltages selected by the selection circuit, outputs a voltage which is the average of the two voltages.