Decoder Circuit Reducing Leakage via Two-High Logic Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern VLSI chips face significant power leakage due to the large number and width of inverters in memory array decode word line drivers, which prior techniques attempt to address by using long channel devices or high voltage threshold devices, but these solutions slow down the decode process.
Innovation Solution
The implementation of a decoder circuit with a pre-decode stage, decode stage, and word line driver stage, utilizing two-high NOR gates and NAND gates, along with multi-output static logic, to reduce current leakage while maintaining operational speed, by placing inverters in the pre-decode stage and using two-high logic gates in the decode and driver stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If long channel devices or high voltage threshold devices are used in word line drivers, then current leakage is reduced, but decode speed is slowed down
Solution Approach 1:
The patent changes the logical structure parameter from traditional inverter-based decoding to two-high logic gate implementation. This structural parameter change allows the circuit to achieve low leakage characteristics without requiring long channel devices or high voltage threshold devices, thus maintaining fast decode speed while reducing current leakage
Solution Approach 2:
The patent extracts and eliminates the inverter stage from the word line driver circuit. By removing inverters and directly implementing two-high logic gates, the patent achieves reduced leakage current without the speed penalty associated with traditional inverter-based designs
2Ease of operation
If inverters are used in word line driver stage, then decoding functionality is achieved, but current leakage increases
Solution Approach 1:
The patent extracts and removes the inverter stage from the word line driver circuit. By eliminating inverters and directly implementing two-high logic gates in the decode stage, the patent achieves the same decoding functionality with significantly reduced current leakage
Solution Approach 2:
Instead of using inverters followed by logic gates (traditional approach), the patent inverts the approach by directly implementing two-high logic gates that perform both inversion and logic functions in a single stage, thereby reducing leakage while maintaining functionality
Data Source
AI summary
A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.