Decoder Circuit Voltage Application Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile semiconductor storage devices, such as flash memory, require high-voltage transistors that increase circuit area and reduce operation speed due to the need for both high-voltage and low-voltage driver circuits.
Innovation Solution
A decoder circuit for semiconductor storage devices that includes a word line selection circuit with voltage application MOS transistors for normal and high-voltage operations, and a level shift circuit that adjusts voltages based on selection states, eliminating the need for high-voltage transistors in the word line selection circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors are used in the word line selection circuit to withstand high voltage during writing or erasing, then the device can perform high-voltage operations, but the circuit area increases and operation speed decreases
Solution Approach 1:
The patent divides the transistor usage into two segments: high-voltage transistors are used only in the driver circuit for high-voltage operations (writing/erasing), while low-voltage transistors are used in the word line selection circuit for normal operations (reading). This segmentation allows each circuit portion to use the appropriate transistor type, preventing the entire decoder circuit from requiring large-area high-voltage transistors.
Solution Approach 2:
The patent applies different transistor characteristics to different locations within the decoder circuit. The driver circuit (which requires high-voltage withstanding) uses high-voltage transistors, while the word line selection circuit (which prioritizes speed and area efficiency) uses low-voltage transistors. This local differentiation optimizes overall circuit performance by placing the right component characteristics in the right locations.
2Reliability
If high-voltage transistors are used in the word line selection circuit, then the device can perform high-voltage operations, but the operation speed decreases
Solution Approach 1:
The patent segments the operational requirements by function: the driver circuit handles high-voltage operations requiring robust transistors, while the word line selection circuit handles fast switching operations requiring speedy transistors. This functional segmentation ensures that speed-critical paths use optimized low-voltage transistors.
Solution Approach 2:
The patent optimizes transistor selection locally based on circuit function. Low-voltage transistors with superior speed characteristics are placed in the word line selection circuit where fast operation is critical, while high-voltage transistors are placed only in the driver circuit where voltage withstanding is critical.
3Adaptability or versatility
If both high-voltage driver circuit and low-voltage driver circuit are included to handle different operations, then the device can perform both high-voltage and low-voltage operations, but the circuit area increases
Solution Approach 1:
The patent creates a unified decoder circuit structure where a single word line selection circuit can serve both high-voltage and low-voltage operations. By using low-voltage transistors in the selection circuit and controlling their switching through appropriate driver circuits, the same circuit infrastructure handles multiple operation modes without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The patent merges the high-voltage and low-voltage operation handling into a single integrated decoder circuit. The driver circuit and word line selection circuit work together as a unified system, where the selection circuit uses low-voltage transistors for both high-voltage and low-voltage operations, reducing the total circuit area compared to having completely separate circuits.
Data Source
AI summary
The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor.