Dynamic Decoder Clock Frequency Control for Memory Error Correction
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Solution Overview
Problem
Current memory systems face inefficiencies in power consumption and decoding time due to fixed operating clock frequencies, which do not adapt effectively to varying numbers of error bits in data read from non-volatile memory, leading to suboptimal performance and increased power usage.
Innovation Solution
A memory system with a control unit that predicts the number of error bits and determines the optimal operating clock frequency and voltage for the decoder based on predicted decoding time, allowing for dynamic adjustment to meet requested reading times while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fixed high clock frequency is used for the decoder, then decoding speed is improved, but power consumption increases
Solution Approach 1:
The decoder operates at multiple clock frequencies (first, second, and third frequencies) rather than a fixed frequency. The control unit dynamically selects the appropriate frequency based on the number of error bits detected in the received word, allowing the system to adapt its operating speed to the actual decoding requirements and minimize power consumption.
Solution Approach 2:
The system changes the operating clock frequency parameter of the decoder based on the error bit count. When fewer error bits are detected, a lower clock frequency is used to reduce power consumption. When more error bits are present, a higher clock frequency is selected to ensure decoding completion within the required time.
2Use of energy by moving object
If a fixed low clock frequency is used for the decoder, then power consumption is reduced, but decoding time increases
Solution Approach 1:
The decoder dynamically adjusts its clock frequency based on the decoding task requirements. The control unit monitors the number of error bits and selects from multiple available frequencies to ensure that decoding is completed within the requested time while minimizing power consumption.
Solution Approach 2:
The system uses feedback from the error bit detection process to determine the appropriate clock frequency. The control unit receives information about the number of error bits in the received word and uses this feedback to select the optimal operating frequency for the decoder.
3Loss of time
If the clock frequency is increased to meet requested decoding time, then decoding time is reduced, but power consumption increases
Solution Approach 1:
The system has multiple clock frequency parameters available (first, second, and third frequencies). The control unit selects the appropriate frequency parameter based on the relationship between the number of error bits and the requested decoding time, changing the frequency parameter to optimize the balance between decoding speed and power consumption.
Data Source
AI summary
According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.