Decoder Error Indication Logic for DTMB Transport Streams

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Solution Overview

Problem

DTV receivers complying with the DTMB standard face unreliable error detection and correction due to the poor error detection and correction capability of BCH decoders, leading to suboptimal performance in identifying and handling error packets in the transport stream.

Innovation Solution

A signal processing apparatus comprising an inner-code decoder, an outer-code decoder, an error detection unit, and decision logic is used to perform error detection and set reliable error indication information, leveraging the LDPC decoder and BCH decoder to correct error bits and generate accurate error indication signals, even with limited error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If BCH decoder is used for error detection and correction in DTMB standard, then decoding can be performed, but error detection and correction capability is poor leading to unreliable error indication

Engineering Contradiction:
Improveerror indication reliabilityVSAvoiderror detection capability
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

An error detection unit is introduced as an intermediary component between the outer-code decoder and the backend processor. This unit performs additional error detection on the decoded data and generates accurate error indication information, mediating the unreliable output of the BCH decoder to provide reliable error status to the backend processor.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The error detection unit provides feedback about the actual error status of decoded data by performing parity checks or other error detection codes. This feedback mechanism allows the system to identify when the BCH decoder has failed to detect or correct errors, enabling reliable error indication despite the decoder's limitations.

Inventive Principle:
Principle #23Feedback

2Device complexity

If BCH decoder with limited correction capability is used, then device complexity is reduced, but error correction performance deteriorates

Engineering Contradiction:
Improvedecoder complexityVSAvoiderror correction reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system merges multiple error handling mechanisms: the BCH decoder's correction capability is combined with the error detection unit's verification capability. This combination allows the system to maintain relatively simple decoder hardware while achieving reliable error correction through the collaborative work of both components.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8225166B2Signal processing apparatus for setting error indication information according error detection result of outer-code decoder output and related method thereof
Publication Date: 2012.07.17 MEDIATEK INC
  • US8225166B2 patent drawing
  • US8225166B2 patent drawing
  • US8225166B2 patent drawing

AI summary

A signal processing apparatus is provided. The signal processing apparatus includes an inner-code decoder, an outer-code decoder, and an error detection unit. The inner-code decoder decodes an input data stream to generate a first output data stream, wherein the input data stream is coded using a concatenated coding scheme including an outer coding and an inner coding. The outer-code decoder decodes the first output data stream to generate a second output data stream. The error detection unit performs an error detection upon the second output data stream to generate an error detection result. The decision logic sets error indication information of the second output data stream according to at least the error detection result.