3D Crosspoint Memory Decoder Floating Deselected Lines
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Solution Overview
Problem
The high energy expenditure in decoder addressing for 3D crosspoint memory arrays is a significant challenge due to the need to change the gate biases of multiple transistors from an idle state to select or deselect address lines, leading to increased energy consumption and reduced efficiency.
Innovation Solution
The proposed solution involves a decoder circuitry that biases selected address lines to a positive or negative voltage without changing the biases of deselected address lines from their idle state, thereby reducing the energy required for addressing by floating deselected address lines to a reference ground voltage and minimizing the need to toggle gate biases of PMOS or NMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate biases of multiple transistors are changed from idle state to select/deselect address lines, then address line selection is achieved, but energy consumption increases
Solution Approach 1:
The decoder switches are segmented into two independent groups: selected switches that connect address lines to voltage sources, and deselected switches that connect address lines to ground. This segmentation allows independent control of each group's gate biases, enabling the deselected group to remain in idle state while only the selected group undergoes bias changes, thereby reducing overall energy consumption.
Solution Approach 2:
The gate biases of the deselected switches are pre-configured to connect address lines to ground in the idle state. This preliminary action ensures that when address lines need to be deselected, no additional bias changes are required for the deselected switches, as they are already in the correct state. Only the selected switches require bias changes, minimizing energy expenditure.
2Reliability
If gate biases are changed to deselect address lines, then address line deselection is achieved, but energy expenditure increases
Solution Approach 1:
The decoder switches are divided into selected and deselected groups with independent gate bias control. The deselected group maintains a fixed idle bias that continuously connects address lines to ground, eliminating the need for repeated bias changes during deselection operations. This segmentation isolates the energy-consuming operations to only the selected switches.
Solution Approach 2:
The deselected switches are configured to automatically maintain address lines in the deselected state through their idle bias configuration. This self-service mechanism ensures continuous deselection without requiring active control or additional energy expenditure, as the idle bias inherently performs the deselection function.
3Reliability
If multiple transistors require gate bias changes from idle state, then address line selection is achieved, but power consumption increases
Solution Approach 1:
The decoder is segmented into selected and deselected switch groups with independent bias control. This allows the stationary power consumption of the deselected group to be minimized by maintaining a fixed idle bias, while only the selected group experiences dynamic power consumption during addressing operations.
Solution Approach 2:
The gate bias parameters are changed selectively: the deselected switches maintain a constant idle bias parameter, while only the selected switches undergo parameter changes during addressing. This selective parameter change reduces both dynamic and static power consumption across the entire decoder circuitry.
Data Source
AI summary
A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.