Decoder Circuit Layout With Substrate Isolation Against Latch-Up
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current decoder circuits in display devices are prone to latch up effects due to interference between CMOS transistors, which can lead to instability and malfunction.
Innovation Solution
The decoder circuit is designed with logic circuit groups arranged sequentially along a first direction and interconnected, featuring N-type and P-type transistors with substrate isolation regions on both sides of the channel region, and vias arranged along a second direction for interconnection, ensuring a sufficient distance between adjacent transistors of different types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors are arranged in conventional decoder circuits, then the circuit can perform decoding functions, but interference between transistors causes latch up effects and reduces circuit stability
Solution Approach 1:
The decoder circuit is divided into multiple logic circuit groups arranged in a matrix structure, with each group containing separated N-type and P-type transistor regions. This segmentation isolates interfering transistors while maintaining decoding functionality through the organized group structure.
Solution Approach 2:
Substrate isolation regions are selectively positioned between adjacent N-type and P-type transistors to provide localized electrical isolation. This creates different electrical properties in different regions of the circuit, preventing interference while allowing normal operation within each transistor region.
2Reliability
If substrate isolation regions are added between transistors, then transistor interference is reduced, but circuit area increases
Solution Approach 1:
The circuit is segmented into logic circuit groups where substrate isolation regions are strategically placed only where needed between N-type and P-type transistors. This segmented approach provides isolation where necessary while minimizing the total area occupied by isolation structures.
Solution Approach 2:
Adjacent substrate isolation regions are merged to form shared isolation structures that serve multiple transistors simultaneously. This reduces the total number of isolation regions needed compared to providing individual isolation for each transistor pair.
Data Source
AI summary
A decoder circuit and a display device are provided, which belong to the technical field of electronics. In each logic circuit group included in the decoder circuit, N-type transistors and P-type transistors are both arranged along a second direction, the N-type transistors and the P-type transistors are arranged along a first direction intersected with the second direction, substrate isolation regions of any transistor are disposed on two sides of the transistor in the first direction, and the substrate isolation region is provided with vias arranged along the second direction. In this way, the P-type transistor and the N-type transistor can be separated by the substrate isolation region with vias, so that a distance between the P-type transistor and the N-type transistor adjacent to each other is greater than a distance between two adjacent transistors of the same type (e.g., N-type transistors or P-type transistors).