Decoder Circuit Shortening and Puncturing for Lower Memory Access Power
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Solution Overview
Problem
Traditional decoder circuits and flash memory controllers face challenges in meeting system-level memory bandwidth requirements due to process yield limitations, leading to high power consumption during simultaneous reading and writing operations, especially in high-noise environments like iterative decoding calculations.
Innovation Solution
A decoder circuit with a memory circuit, variable node circuit, variable-to-check circuit, check node circuit, and syndrome calculation circuit is implemented, which includes a shortening and puncturing mechanism to store and manage data portions based on a decoding calculation schedule, reducing the frequency of reading and writing by using system default values for punctured or shortened data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all small physical memories operate at the same time to meet system-level bandwidth requirements, then memory bandwidth is improved, but power consumption increases significantly
Solution Approach 1:
The decoder circuit segments the processing of codewords into iterative decoding steps, where only actively needed memory locations are accessed in each iteration rather than all memory locations simultaneously. This segmentation allows the system to maintain necessary bandwidth while reducing peak power consumption by dividing the simultaneous access requirement into sequential access patterns across multiple iterations.
Solution Approach 2:
The memory access pattern implements periodic action through iterative decoding, where memory locations are accessed in repeated cycles rather than all at once. Each iteration accesses a subset of memory locations, and this periodic access pattern reduces the instantaneous power consumption while maintaining the overall data throughput required for system-level bandwidth performance.
2Measurement precision
If iterative decoding calculation is performed in high-noise environment, then decoding accuracy is improved, but power consumption increases
Solution Approach 1:
The decoder circuit applies partial action by performing iterative decoding calculations only for the necessary number of iterations required to achieve adequate decoding accuracy, rather than continuously executing full decoding cycles. This allows the system to achieve sufficient measurement precision while avoiding excessive power consumption from redundant calculations, especially important in high-noise environments where convergence may be slower.
3Use of energy by moving object
If shortening and puncturing settings are applied to free up storage positions, then memory access frequency is reduced, but device complexity increases
Solution Approach 1:
The decoder circuit implements preliminary action by pre-configuring shortening and puncturing settings before the actual decoding process begins. These settings pre-identify which storage positions can be freed up, allowing the system to reduce memory access frequency and power consumption without requiring complex real-time decisions during decoding. The preliminary configuration simplifies the overall control logic despite the added structural elements.
Data Source
AI summary
A decoding method of a decoder circuit includes: using a memory circuit to receive input data; using the input data to generate or update a variable-to-check message and a log-likely ratio; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message, so as to calculate and update the variable-to-check message and the log-likely ratio; performing a hard decision according to the log-likely ratio; storing multiple data portions of the input data into multiple storage positions of the memory circuit in response to a decoding calculation schedule; and controlling storage position(s) of the memory circuit to be empty for the shortening setting or puncturing setting.