Iterative Decoder Memory Layout for Higher Density and Fewer Ports
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Solution Overview
Problem
Conventional memory arrangements for iterative decoders, such as Low Density Parity Check (LDPC) decoders, face challenges in memory density and port constraints, leading to larger memory areas and inefficiencies in data processing.
Innovation Solution
The proposed solution involves a memory module with a single R memory component and two Q memory banks, where the channel detector can access both R and Q data, using a Soft Output Viterbi Algorithm (SOVA) decoder and extrinsic channel log-likelihood-ratio memory, allowing for improved memory density by combining memory banks and minimizing the need for additional ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate memory banks are used to store R data and Q data for current and previous codewords, then data access reliability is improved, but memory area and device complexity increase
Solution Approach 1:
The patent combines multiple separate memory banks into a single unified memory structure. Specifically, it uses one R memory to store both current and previous codeword R data, and one Q memory to store both current and previous codeword Q data. This merging reduces the total memory area while maintaining reliable data access through careful timing and address management.
Solution Approach 2:
The unified R memory and Q memory serve multiple functions: they store data for both current and previous codewords, support both read and write operations, and enable parallel processing of multiple codewords. This multi-functionality reduces the need for separate dedicated memory banks for each function.
2Productivity
If multiple memory ports are provided to access R and Q data simultaneously, then data processing speed is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent employs dynamic address management and timing control to manage memory access. Instead of providing multiple simultaneous ports, it uses dynamic addressing schemes and coordinated timing to allow the channel detector to access both R and Q data efficiently through a single port, reducing hardware complexity while maintaining processing speed.
Solution Approach 2:
The memory access pattern follows periodic cycles where the channel detector alternates between accessing R data and Q data in an organized sequence. This periodic access pattern allows efficient data retrieval without requiring multiple simultaneous ports, as the single port is systematically allocated to different data access needs.
3Quantity of substance
If a single R memory component is used to store both current and previous codeword data, then memory density is improved, but access time and productivity may worsen
Solution Approach 1:
The patent resolves the access time issue by introducing the time dimension through coordinated timing control. While the single R memory physically stores both current and previous codeword data (improving density), the system uses time-multiplexed access with carefully coordinated read/write timing to ensure that data is retrieved without delay, effectively managing the trade-off between density and access speed.
Data Source
AI summary
The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.