Hierarchical Decoder Structure for Memory Column Selection
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Solution Overview
Problem
Existing memory architectures face challenges in optimizing decoder structures for reduced power consumption, area occupancy, and minimizing signal drops and spurious enabling signals, which affect memory speed and performance.
Innovation Solution
The proposed decoder structure organizes NMOS transistors into sub-column groups across multiple levels, with precharge transistors forming inverter blocks to reduce the total number of transistors and prevent signal drops, using PMOS precharge transistors to maintain node voltages and avoid charge sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a column decoder includes a plurality of NMOS transistors coupled to N bit lines for selecting columns, then column selection capability is achieved, but power consumption and area occupancy increase
Solution Approach 1:
The patent divides the column decoder into multiple hierarchical levels (first level, second level, third level) with different numbers of transistors at each level. The first level has the most transistors for fine-grained selection, while subsequent levels have progressively fewer transistors for coarser selection, enabling efficient column selection with reduced overall transistor count and power consumption.
Solution Approach 2:
The patent introduces a hierarchical structure with multiple decoding levels, transforming the traditional flat decoder architecture into a multi-dimensional hierarchy. This allows the decoder to select columns through a sequence of coarser-to-finer granularity levels, reducing the total number of transistors needed compared to a single-level decoder.
2Adaptability or versatility
If a column decoder includes a plurality of NMOS transistors coupled to N bit lines for selecting columns, then column selection capability is achieved, but area occupancy increases
Solution Approach 1:
The patent segments the decoder into hierarchical levels with decreasing transistor counts. By organizing transistors in this segmented hierarchy rather than a uniform structure, the patent reduces the total area required while maintaining full column selection capability across all N bit lines.
Solution Approach 2:
The hierarchical multi-level structure transforms the traditional two-dimensional array of transistors into a three-dimensional hierarchical arrangement. This dimensional transformation allows for more efficient space utilization and reduced area occupancy while preserving the full column selection function.
3Reliability
If precharge transistors are added to form inverter blocks for preventing signal drops, then signal stability improves, but device complexity increases
Solution Approach 1:
The patent introduces precharge transistors as intermediary elements that form inverter blocks between the hierarchical decoder levels and the bit lines. These precharge transistors act as mediators to prevent signal drops and spurious enabling signals by providing controlled precharging paths, thereby improving signal stability without requiring complete redesign of the decoder architecture.
Solution Approach 2:
The patent modifies the electrical parameters of the decoder by introducing precharge transistors with specific gate control signals. These parameter changes enable the precharge transistors to regulate node voltages and prevent signal degradation, improving reliability through controlled electrical parameter adjustment rather than fundamental structural changes.
Data Source
AI summary
A decoder structure for selecting a column of memory cells in a memory architecture includes an array of decoder cells organized into different rows. Each row includes a plurality of sub-column groups of decoder cells configured to receive a same input signal. Each sub-column group of decoder cells of a row is coupled to a sub-column group of decoder cells of a subsequent row. The decoder structure further includes a plurality of precharge transistors connected to the decoder cells of a row so as to form a plurality of inverter blocks.