Decoder Circuit Memory Partitioning for Low-Power Read/Write
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Solution Overview
Problem
Conventional decoder circuits experience excessive power consumption due to the large number of bits read and written from memories during sum calculations, primarily in variable node units.
Innovation Solution
A decoder circuit with a novel algorithm mechanism that reduces memory read/write operations by storing channel values as sign bits and magnitude bits, and only writing when changes occur, using barrel shifters to convert values between domains, and a decision bit output unit for hard decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional variable node units read/write bit information from memories during sum calculations, then decoding operations can be performed, but power consumption becomes excessive due to the large number of bits accessed
Solution Approach 1:
The patent segments the bit information into two distinct parts: sign bits and magnitude bits. This segmentation allows the system to store only the magnitude bits in memory while keeping sign bits in registers, thereby reducing the number of bits that need to be read from and written to memory during decoding operations, which directly reduces power consumption while maintaining full decoding functionality.
Solution Approach 2:
The patent introduces a new dimensional organization of data by separating sign and magnitude components into different storage locations (registers vs. memory). This dimensional change allows the system to access sign bits quickly from registers without incurring memory access power costs, thus reducing overall power consumption while preserving the ability to perform complete sum calculations.
2Measurement precision
If all bit information is stored in memory to maintain decoding accuracy, then decoding precision is maintained, but the number of memory read/write operations increases leading to higher power consumption
Solution Approach 1:
The patent extracts the sign bits from the memory storage and places them in registers. This extraction allows the system to maintain full decoding accuracy by having immediate access to sign information without requiring memory read/write operations, thereby reducing power consumption while preserving decoding precision.
Solution Approach 2:
The patent performs preliminary separation of sign and magnitude bits during the data loading phase, storing sign bits in registers before the actual decoding operations begin. This preliminary action ensures that sign information is readily available during sum calculations without requiring additional memory access, thus maintaining accuracy while reducing power consumption during the decoding process.
Data Source
AI summary
A decoding method includes: providing channel value memory to store input data as a channel value; providing sign memory to store a sign value; providing gradient descent bit memory to store differential information of a channel value; providing variable node unit to generate a first output value and a second output value according to the channel value; converting first output value into a converted first output value from variable node domain into check node domain; providing check node unit to generate check-to-variable message according to the converted first output value or the sign value stored in the sign memory; converting the check-to-variable message into a converted check-to-variable message from check node domain into variable node domain and transmitting the converted check-to-variable message into the variable node domain; and, deciding output data according to channel value and differential information stored in gradient descent bit memory.