Iterative Decoder Message Passing with Fewer Wires and Lower Power
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Solution Overview
Problem
Iterative error correcting decoders, such as LDPC decoders, face challenges in reducing power consumption and complexity due to high numbers of wires and long wire lengths, which limit their performance and increase bit error rate (BER) despite increased iterations, especially with low-bit resolution message passing.
Innovation Solution
The proposed iterative decoder reduces wiring by transferring multiple bits (i>1) over fewer wires using multiplexing and bidirectional transmission, and employs XOR gates and shift registers to transmit only changed data, minimizing power consumption by reducing switching activity and using non-return to zero (NRZ) transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parallel processing is used to increase the number of iterations, then BER performance is improved, but the number of wires and area increase significantly
Solution Approach 1:
Multiple bit-lines are merged into a single wire by transmitting multiple bits sequentially over the same physical connection. The patent combines multiple parallel data streams into fewer wires by using time-division multiplexing, where different bit-lines share the same physical wire at different time slots, thereby reducing the total wire count while maintaining parallel processing capability
Solution Approach 2:
The system dynamically switches between different transmission modes (parallel vs. reduced-wire mode) based on operational requirements. The patent implements dynamic control logic that can switch between transmitting multiple bits in parallel over separate wires or serializing them over fewer wires, allowing the system to adapt to different performance and resource requirements
2Reliability
If high-bit resolution message passing is used, then BER performance is improved, but power consumption increases
Solution Approach 1:
The patent extracts and transmits only the essential or changed information rather than complete high-resolution messages. By identifying and transmitting only the significant bits that contain useful information or have changed since the previous iteration, the system maintains decoding performance while reducing the number of bits transmitted and the associated power consumption
Solution Approach 2:
The system dynamically adjusts the message resolution parameter based on iteration number and convergence criteria. Early iterations use lower resolution to reduce power consumption, while later iterations may increase resolution if convergence has not been achieved, optimizing the trade-off between performance and power usage throughout the decoding process
3Reliability
If the number of iterations is increased, then BER performance is improved, but power consumption and area increase
Solution Approach 1:
The patent implements periodic reduction of transmission activity based on convergence detection. When the decoder detects that messages have converged (no significant changes between iterations), it periodically reduces or stops transmission activity, allowing the system to perform multiple iterations when needed while conserving power when convergence is achieved
Solution Approach 2:
The system performs partial message passing by transmitting only a subset of messages or only the changed portions of messages in each iteration. Rather than fully updating all messages every iteration, the patent selectively updates only those messages that have changed or are most likely to contribute to convergence, reducing the total computational and power resources required
Data Source
AI summary
A decoder and method for implementing an iterative error correcting decoder are provided for decoding a codeword consisting of a N-bit messages. In one implementation, the decoder includes a first set of nodes, and a second set of nodes, each having N bits of resolution. Each node of the second set is coupled to at least one node of the first set, each node of the second set being coupled to a node of the first set by a corresponding set of M wires. Each of the first set of nodes is operable to transfer the bits of a given N-bit message of the codeword over the corresponding set of M wires to a coupled node of the second set during a single iteration cycle, each of the M wires carrying i bits, where N is an integer greater than M, and N=M*i.