Shared Instruction Decoder Micro-Operation Segmentation
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Solution Overview
Problem
In data processing systems with shared instruction decoders for multiple threads, a stall in one fetch unit can cause the entire decoder to stall, preventing other fetch units from receiving decoded micro-operations, leading to reduced processing performance.
Innovation Solution
Implementing a shared instruction decoder that generates each micro-operation of a complex program instruction individually in response to separate decode requests from fetch units, allowing the decoder to switch between instructions partway through processing and resume when the stalled unit becomes active.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the shared instruction decoder generates all micro-operations for a complex program instruction in successive cycles in response to a single decode request, then the decoder ensures complete decoding of the instruction, but the decoder stalls when one fetch unit stalls, preventing other fetch units from receiving micro-operations and reducing processing performance
Solution Approach 1:
The patent segments the decoding of a complex program instruction into multiple independent micro-operations, where each micro-operation can be decoded and fetched separately. Instead of treating the complex instruction as a single atomic unit that must be fully decoded before any micro-operations are issued, the system divides it into individual micro-operations that can be processed independently by different fetch units, resolving the contradiction between complete decoding and maintaining processing throughput.
Solution Approach 2:
The patent implements dynamic decoding where the instruction decoder can switch between decoding different micro-operations of a complex instruction based on the readiness state of fetch units. When one fetch unit stalls, the decoder dynamically adapts by decoding micro-operations for other ready fetch units, rather than statically committing to a fixed decoding sequence. This dynamic behavior maintains decoder utilization and processing performance while ensuring complete decoding eventually occurs.
2Stability of the object's composition
If the shared instruction decoder is committed to finishing all micro-operations for a complex program instruction before switching to another instruction, then the decoder maintains instruction integrity, but the decoder remains inactive during fetch unit stalls, increasing the number of inactive cycles
Solution Approach 1:
The patent applies preliminary action by pre-decoding micro-operations and storing them in a micro-operation cache before they are needed by fetch units. When a fetch unit is ready, it can quickly retrieve pre-decoded micro-operations from the cache without causing the decoder to stall. This preliminary preparation maintains instruction integrity while reducing decoder inactive cycles, as the decoder can work ahead and prepare micro-operations in advance.
Solution Approach 2:
The patent introduces a micro-operation cache as an intermediary between the instruction decoder and fetch units. This cache buffer allows the decoder to operate independently of fetch unit readiness, storing decoded micro-operations for later retrieval. The intermediary cache decouples the decoder's operation from fetch unit stalls, maintaining instruction integrity while minimizing decoder idle time by allowing the decoder to continue working on pending instructions.
3Device complexity
If multiple fetch units share a single instruction decoder, then the system reduces hardware complexity, but a stall in one fetch unit propagates to the decoder and blocks other fetch units from receiving micro-operations
Solution Approach 1:
The patent segments the complex instruction into independent micro-operations that can be decoded and fetched separately. This segmentation allows the shared decoder to service multiple fetch units independently, with each fetch unit receiving its required micro-operations without being blocked by stalls in other fetch units. The segmentation maintains low hardware complexity by using a single decoder while improving productivity through independent micro-operation delivery.
Solution Approach 2:
The patent ensures continuity of useful action by allowing the shared instruction decoder to continuously decode micro-operations for different fetch units based on their readiness state. When one fetch unit stalls, the decoder continues to perform useful work by decoding micro-operations for other ready fetch units rather than idle. This continuous operation maintains high micro-operation delivery rates while preserving the hardware efficiency of a shared decoder architecture.
Data Source
AI summary
A data processing apparatus 2 has processing circuitry 4 which can process multiple parallel threads of processing. A shared instruction decoder 30 decodes program instructions to generate micro-operations to be processed by the processing circuitry 4. The instructions include at least one complex instruction which has multiple micro-operations. Multiple fetch units 8 are provided for fetching the micro-operations generated by the decoder 30 for processing by the processing circuitry 4. Each fetch unit 8 is associated with at least one of the threads. The decoder 30 generates the micro-operations of a complex instruction individually in response to separate decode requests 24 triggered by a fetch unit 8, each decode request 24 identifying which micro-operation of the complex instruction is to be generated by the decoder 30 in response to the decode request 24.