High-Voltage Decoder Circuit Using Series PMOS Load Splitting
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Solution Overview
Problem
Conventional decoder circuits in semiconductor memory devices face issues such as increased power consumption, reliability degradation, and layout area expansion due to high power supply voltage limitations, as well as increased design costs and potential noise sensitivity, particularly in the second conventional circuit which requires extra wiring and half latch circuits.
Innovation Solution
The proposed decoder circuit employs a load current generating portion with two PMOS transistors coupled in series to supply high voltage to a potential setting node, allowing the high voltage to be set above the ON-state breakdown voltage of each PMOS transistor without reliability degradation, reducing the need for half latch circuits and extra wiring, and optimizing control signal settings for lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PMOS transistor is used to supply high voltage, then the circuit structure is simple, but the high voltage exceeds the ON-state breakdown voltage causing reliability degradation
Solution Approach 1:
The single PMOS transistor is divided into two PMOS transistors (first PMOS transistor and second PMOS transistor) connected in series. This segmentation allows the high power supply voltage to be distributed across both transistors, ensuring that the voltage across each transistor does not exceed its ON-state breakdown voltage, thereby maintaining reliability while preserving circuit simplicity
2Speed
If the high power supply voltage is increased to improve performance, then the decoding speed improves, but the power consumption increases due to increased load current
Solution Approach 1:
The invention changes the circuit configuration from a single PMOS transistor to two PMOS transistors in series, which alters the voltage distribution parameters. This allows the high power supply voltage to be effectively utilized for fast decoding while the series connection inherently limits the load current, thus reducing power consumption compared to a single transistor configuration
3Speed
If the high power supply voltage is increased to improve performance, then the decoding speed improves, but the layout area increases due to larger transistor sizes
Solution Approach 1:
By segmenting the single PMOS transistor into two series-connected PMOS transistors, the voltage stress on each transistor is reduced, allowing the use of smaller transistor sizes that still achieve the required decoding speed. This segmentation strategy reduces the overall layout area while maintaining performance
Data Source
AI summary
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.