Shared Decoder Pool Initialization to Avoid Head-of-Line Blocking
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Solution Overview
Problem
Existing data storage devices face challenges with unpredictable decoding times due to iterative error correcting codes, leading to head-of-line blocking and degraded quality of service (QoS) when using a single decoder, which can be exacerbated by high bit error rates (BER) events.
Innovation Solution
Implementing a parallelized syndrome calculation and bit error rate estimation scan (BES) operation in conjunction with a shared decoder pool, allowing syndrome calculation to be performed in parallel with data input, thereby reducing latency and throughput bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single decoder is used for error correction, then device complexity is reduced, but decoding throughput and quality of service deteriorate due to unpredictable decoding times and head-of-line blocking
Solution Approach 1:
The decoder is segmented into multiple independent decoder cores (first decoder core, second decoder core, etc.) that can operate in parallel. Each core can independently decode different data blocks, eliminating head-of-line blocking and improving overall decoding throughput while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The syndrome calculation unit performs preliminary syndrome calculations on incoming data blocks before they reach the decoder cores. This preliminary processing prepares the data in advance, allowing decoder cores to immediately begin decoding operations without waiting for data preparation, thereby improving throughput and reducing latency
2Productivity
If multiple decoder cores are added to improve throughput, then decoding productivity increases, but device complexity and silicon cost increase
Solution Approach 1:
Multiple decoder cores are merged into a unified decoder pool architecture that shares common resources such as the syndrome calculation unit, input buffers, and control logic. This merging approach enables parallel decoding operations to improve throughput while avoiding the full silicon cost of completely independent decoders, as shared resources reduce overall complexity
Solution Approach 2:
The syndrome calculation unit and buffer memory are designed as universal resources that serve multiple decoder cores simultaneously. These multi-functional components can dynamically allocate resources to different cores based on workload demands, improving throughput while minimizing the additional silicon required compared to dedicated per-core resources
3Device complexity
If syndrome calculation is performed sequentially after data input, then device complexity is minimized, but decoding latency increases due to sequential processing
Solution Approach 1:
The syndrome calculation unit performs syndrome calculations on data blocks as they are being input to the decoder, rather than waiting for complete data input. This preliminary calculation of syndromes in parallel with data input significantly reduces decoding latency by preparing error correction information in advance, while maintaining relatively simple device architecture through efficient resource utilization
Data Source
AI summary
A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.