Shared Decoder Pool Pipelining to Prevent Head-of-Line Blocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data storage devices using shared decoder pools experience head-of-line blocking, leading to delayed decoding of data blocks and reduced quality of service due to unpredictable decoding times and high latency in iterative decoding operations.
Innovation Solution
Parallelize the syndrome calculation and data input process in the decoder's input buffer to avoid head-of-line blocking, allowing the decoder to operate efficiently by completing syndrome calculations concurrently with data input, thereby maintaining pipeline benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential decoding operations are used in shared decoder pools, then resource utilization is improved, but decoding latency increases due to head-of-line blocking
Solution Approach 1:
The patent performs syndrome calculation in advance during the data input phase, before the actual decoding operation begins. By pre-computing the syndrome while data is being written to the input buffer, the decoder is prepared for immediate decoding execution, eliminating waiting time and head-of-line blocking effects.
Solution Approach 2:
The patent transforms the traditional sequential decoding process into a parallel operation by executing syndrome calculation and data input simultaneously in different time dimensions. This pipelining approach allows multiple operations to overlap, effectively adding a temporal dimension to the decoding process that resolves the blocking issue.
2Reliability
If iterative decoding operations are performed, then error correction capability is improved, but decoding time becomes unpredictable and latency increases
Solution Approach 1:
By calculating the syndrome beforehand during data input, the patent separates the error detection preparation from the actual iterative decoding process. This preliminary action provides advance information about error conditions, allowing the iterative decoder to start with optimized parameters and potentially reduce the number of iterations required.
Solution Approach 2:
The pre-calculated syndrome serves as feedback information that guides the iterative decoding process. By having the syndrome ready before decoding begins, the system can make informed decisions about decoding strategy and convergence criteria, improving time predictability while maintaining error correction capability.
3Productivity
If decoder pool size is increased to reduce blocking, then decoding throughput is improved, but device complexity and silicon cost increase
Solution Approach 1:
The patent eliminates the need for multiple parallel decoder engines by implementing preliminary syndrome calculation. A single decoder can efficiently handle sequential requests because each decoding operation is pre-prepared with its syndrome information, removing the performance penalty that would otherwise require additional decoder instances.
Solution Approach 2:
By overlapping syndrome calculation with data input through pipelining, the patent ensures continuous productive use of the decoder resource. The decoder remains actively engaged in useful work without idle waiting periods, achieving high throughput with a single decoder engine rather than requiring multiple engines to mask latency.
Data Source
AI summary
A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.