Decoder Physical Position Conversion for Memory Wear Leveling

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Solution Overview

Problem

Existing semiconductor memory devices face reliability issues due to uneven wear and tear on memory cells, leading to reduced performance and lifespan, as certain memory cells are accessed more frequently than others, causing premature wear-out.

Innovation Solution

A decoder system that converts the physical position of memory cells based on an address count, switching cells from a primary memory area to a secondary area when the access count exceeds a predetermined value, thereby distributing the usage more evenly and preventing excessive access to any single memory cell.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory cells are accessed frequently at fixed physical positions, then access speed is improved, but reliability deteriorates due to uneven wear on memory cells

Engineering Contradiction:
Improveaccess speedVSAvoidmemory cell reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements dynamic address translation that changes the mapping between logical addresses and physical memory cell positions based on access frequency. When a memory cell is accessed a certain number of times, its mapping is changed to a different physical position, distributing wear across multiple cells while maintaining fast access to frequently used data through caching mechanisms.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of physical position mapping dynamically. By monitoring access counts and changing the physical position assignment when thresholds are reached, the system redistributes wear patterns across the memory array while preserving efficient access patterns through the translation layer.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If wear leveling is implemented by converting physical positions, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvememory device reliabilityVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an address translation layer as an intermediary between the host interface and the physical memory array. This translation layer includes components such as a mapping table, access count counters, and position conversion logic that mediate between logical addresses and physical cell positions, implementing wear leveling without requiring complex modifications to the underlying memory cell structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7929372B2Decoder, memory system, and physical position converting method thereof
Publication Date: 2011.04.19 SAMSUNG ELECTRONICS CO LTD
  • US7929372B2 patent drawing
  • US7929372B2 patent drawing
  • US7929372B2 patent drawing

AI summary

A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.