Context-Adaptive Binary Arithmetic Decoder Low Latency Prefetch

The patent implements a multi-port context memory that prefetches context variables in advance before they are needed for decoding. The memory system proactively loads context variables into buffer registers during cycles when they are not immediately required, so that when the arithmetic decoder needs them, they are already available. This preliminary action eliminates the two-cycle latency by ensuring context data is ready before the decode operation requires it.

The patent introduces buffer registers as an intermediary between the multi-port context memory and the arithmetic decoder. These buffer registers hold prefetched context variables and provide them to the decoder on demand. The intermediary buffer layer decouples the memory access timing from the decode operation timing, allowing the decoder to operate at full speed without being constrained by memory access latency.

The patent segments the context memory into multiple independent ports, allowing simultaneous access to different context variables. Instead of a single sequential access port, the memory is divided into multiple ports that can be accessed in parallel. This segmentation enables the system to fetch multiple context variables concurrently during the same time period, dramatically improving decode throughput without proportionally increasing overall system complexity.

The patent ensures continuous decoding operation by eliminating wait states through the multi-port memory architecture. While one port is being accessed, other ports can simultaneously prefetch the next required context variables. This continuous operation allows the arithmetic decoder to process binary values at every clock cycle without interruption, maintaining maximum productivity throughout the decoding process.