Distributed Multi-Channel Decoder Scheduling for Lower Buffering

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Solution Overview

Problem

Existing multi-channel decoder systems face inefficiencies due to variable processing times and resource underutilization, leading to high power consumption and die size, especially in systems with a constant input data rate, which requires extensive buffering and increases processing delay.

Innovation Solution

A multi-channel decoder system with distributed scheduling, utilizing a set of unit decoder circuits and a distribution controller to dynamically allocate codewords to available decoder circuits based on availability and quality of service, reducing the number of decoder circuits needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a constant number of decoder circuits are used to handle multiple input channels, then the system structure is simple, but resource underutilization occurs due to variable processing times

Engineering Contradiction:
Improvedecoder circuit structureVSAvoidresource utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system dynamically allocates codewords to decoder circuits based on real-time availability status. Instead of static assignment, the distribution controller continuously monitors which decoder circuits are free and assigns incoming codewords to available circuits, allowing the system to adapt to variable processing times and maximize resource utilization.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Decoder circuits are designed to be universal and can process codewords from any input channel. Rather than having dedicated decoder circuits for each channel, the same pool of decoder circuits serves multiple channels, increasing flexibility and reducing the total number of circuits needed while improving utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If extensive buffering is used to handle variable processing times, then data loss is prevented, but processing delay increases

Engineering Contradiction:
Improvedata completenessVSAvoidprocessing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The distribution controller continuously monitors decoder circuit availability and maintains a steady flow of codeword processing. By keeping decoder circuits continuously busy with available work and using minimal buffering only when necessary, the system prevents data loss while minimizing idle time and processing delays.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The system uses minimal buffering that only stores codewords when absolutely necessary (when all decoders are busy). The distribution controller intelligently manages this small buffer, releasing codewords to decoders as soon as they become available, thereby reducing processing delay while still preventing data loss.

Inventive Principle:
Principle #25Self-service

3Productivity

If more decoder circuits are allocated to handle peak demand, then processing capacity is sufficient, but power consumption and die size increase

Engineering Contradiction:
Improveprocessing capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by stationary object

Solution Approach 1:

The system dynamically adjusts the utilization of decoder circuits based on incoming workload. Instead of having a fixed large number of decoder circuits running continuously, the system activates and utilizes decoder circuits as needed, reducing power consumption when demand is low while maintaining sufficient processing capacity during peak periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Multiple input channels share a common pool of decoder circuits rather than having separate dedicated circuits for each channel. This consolidation reduces the total number of decoder circuits needed, thereby reducing power consumption and die size while maintaining the ability to handle peak demand from multiple channels simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If dedicated decoder circuits are used for each input channel, then channel isolation is maintained, but the number of decoder circuits and die size increase

Engineering Contradiction:
Improvechannel independenceVSAvoiddie size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Decoder circuits are designed to be universal and can process codewords from any input channel. Rather than having dedicated decoder circuits for each channel, the same pool of decoder circuits serves multiple channels, increasing flexibility and reducing the total number of circuits needed while maintaining channel independence through software/control logic management.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system segments the decoding function into a shared pool of universal decoder circuits that can be dynamically assigned to different channels as needed. This segmentation allows channel independence to be maintained through control logic while reducing the physical hardware footprint compared to dedicated circuits for each channel.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12556200B2Multi-channel decoder with distributed scheduling
Publication Date: 2026.02.17 MAXLINEAR INC
  • US12556200B2 patent drawing
  • US12556200B2 patent drawing
  • US12556200B2 patent drawing

AI summary

A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.