Variable Code Rate Decoder Segmented Parity Check Matrix

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Solution Overview

Problem

Existing data processing systems face impracticalities in supporting variable code rates due to complex wiring requirements, especially when using large parity check matrices, making non-layered decoding impractical.

Innovation Solution

The implementation of a data decoder circuit with a constrained H-matrix structure that connects check units to a subset of checks, simplifying routing and allowing for flexible distribution of row weights through overlapping sections, which reduces routing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If non-layered decoding is used with large parity check matrices, then variable code rate support is desired, but wiring complexity becomes impractical

Engineering Contradiction:
Improvevariable code rate supportVSAvoidwiring complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The parity check matrix is divided into multiple sections, with each section processed by a dedicated comparator circuit. Row storage units are organized into groups that feed specific comparators, creating a segmented architecture that reduces overall wiring complexity while maintaining variable code rate support

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoder circuit is designed to handle multiple code rates using the same hardware structure. The routing circuits and comparator circuits can be configured to process different code rates (e.g., 1/2, 2/3, 3/4) without requiring separate dedicated wiring for each rate, making the system universally applicable to various code rates

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a large parity check matrix is utilized, then more comprehensive error correction is achieved, but routing complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidrouting complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The large parity check matrix is segmented into multiple smaller sections that can be processed independently by different comparator circuits. This segmentation maintains the comprehensive error correction capability of the large matrix while reducing the routing complexity by breaking down the processing into manageable chunks

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a sectional dimension to the parity check matrix processing. Instead of processing the entire large matrix in a single routing structure, the matrix is divided into sections along one dimension, allowing parallel processing through multiple comparator circuits and reducing the complexity of individual routing paths

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9384761B1Systems and methods for flexible variable code rate support
Publication Date: 2016.07.05 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9384761B1 patent drawing
  • US9384761B1 patent drawing
  • US9384761B1 patent drawing

AI summary

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for data encoding and decoding.