Decoder Circuit Using Series PMOS for High-Voltage Reliability
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Solution Overview
Problem
Conventional decoder circuits in semiconductor memory devices face issues such as increased power consumption, reliability degradation, and layout area expansion due to high power supply voltage limitations, as well as increased design costs and potential noise sensitivity, particularly in the second conventional circuit which requires extra wiring and half latch circuits.
Innovation Solution
The proposed decoder circuit employs a load current generating portion with two PMOS transistors coupled in series to supply load current to a potential setting node, allowing high voltage to be set without exceeding the ON-state breakdown voltage of each transistor, thereby reducing power consumption and layout area while eliminating the need for half latch circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PMOS transistor is used to supply high voltage, then the circuit structure is simple, but the transistor exceeds its ON-state breakdown voltage causing reliability degradation
Solution Approach 1:
The single PMOS transistor is segmented into two PMOS transistors (first and second PMOS transistors) connected in series. This segmentation divides the high voltage stress across multiple devices, ensuring that no single transistor exceeds its breakdown voltage while maintaining the overall high voltage output capability.
2Speed
If high power supply voltage is used, then the decoding speed is improved, but the power consumption increases
Solution Approach 1:
The circuit dynamically controls the supply of high voltage to the potential setting node based on operational needs. The first PMOS transistor supplies high voltage during non-selected states for fast decoding, while the second PMOS transistor controls the voltage during selected states, enabling dynamic power management that reduces consumption while maintaining speed.
3Object-affected harmful factors
If half latch circuits and extra wiring are added, then the noise sensitivity is reduced, but the layout area and design costs increase
Solution Approach 1:
The invention extracts and eliminates the unnecessary half latch circuits and extra wiring from the conventional decoder design. By using the two-series-PMOS configuration with controlled voltage supply, the circuit achieves noise immunity through proper voltage level management without requiring additional latch circuits or wiring, thereby reducing layout area and design complexity.
Data Source
AI summary
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.