Decoder Sub-Decoding Global Check Node Memory Reliability
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Solution Overview
Problem
Multi-level memory cells in highly-integrated memory devices face reliability issues due to overlapping threshold voltage distributions, leading to increased read failure rates and data errors as the number of bits programmed in each memory cell increases, especially in TLC flash memory devices where charge losses and program disturbances cause neighboring distributions to overlap.
Innovation Solution
A decoder system that performs multiple sub-decoding operations, including first and second sub-decoding on target and candidate data chunks, a third sub-decoding to determine a global check node based on successful data chunks, and a fourth sub-decoding to update local variable nodes using the global check node, repeating these operations based on updated components to improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells are used to increase storage capacity, then integration level and storage density are improved, but reliability decreases and read failure rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the decoding process into multiple stages: first sub-decoding on target data chunk, second sub-decoding on candidate chunks, third sub-decoding to determine global check node, and fourth sub-decoding to update local variable nodes. This segmented approach allows systematic error correction across different data chunks, improving reliability while maintaining high storage capacity in multi-level memory cells
Solution Approach 2:
The patent introduces a global check node dimension that operates across multiple data chunks beyond the individual target chunk. By determining global check nodes from successful chunks and applying them to failed chunks, the system adds a cross-chunk verification dimension that enhances error correction capability without reducing storage density
2Quantity of substance
If the number of bits programmed in each memory cell increases, then storage density is improved, but the distance between threshold voltage distributions decreases causing more overlap and errors
Solution Approach 1:
The patent implements feedback mechanisms where decoding results from candidate chunks provide information back to the target chunk decoding process. The global check node determined from successful decodings feeds back into the fourth sub-decoding operation to update local variable nodes of failed chunks, creating a feedback loop that improves measurement precision in distinguishing threshold voltage distributions
Solution Approach 2:
The patent performs preliminary decoding operations on candidate chunks before finalizing the target chunk decoding. By first attempting to decode candidate chunks and using their results to inform the target chunk decoding, the system prepares correction information in advance, improving the ability to distinguish overlapping threshold voltage distributions
3Reliability
If charge losses and program disturbances occur, then data integrity deteriorates with overlapping distributions, but implementing robust error correction increases decoding complexity
Solution Approach 1:
The patent divides the error correction process into four distinct sub-decoding operations that can be independently executed and optimized. Each sub-decoding stage handles specific aspects of error correction, allowing the system to manage complexity through modular design while maintaining high data integrity through comprehensive error checking across multiple stages
Solution Approach 2:
The patent merges the decoding of target chunks with candidate chunks into a unified multi-stage process. By combining information from multiple chunks and using global check nodes that span across chunks, the system achieves robust error correction for charge losses and program disturbances while sharing computational resources and reducing overall decoding complexity
Data Source
AI summary
An operation method of a decoder may include: performing a first sub-decoding operation on a target data chunk; performing a second sub-decoding operation on candidate chunks and a chip-kill chunk; performing a third sub-decoding operation to determine a global check node; performing a fourth sub-decoding operation to infer and update local variable nodes of the target data chunk and local variable nodes of a data chunk from the global check node; and repeating the first to fourth sub-decoding operations once by a set number of times based on components of the updated local variable nodes.