Decoding Circuit Layout for Single-Bit Error Correction
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Solution Overview
Problem
Existing error detection and correction methods using error-correcting codes (ECC) are complex and require large circuits, making them inefficient for reliable data transmission and storage, especially in scenarios where single-bit and double-bit errors need to be accurately detected and corrected.
Innovation Solution
A semiconductor device with a decoding circuit comprising (n−1) 2-bit checking units and an all-bit checking unit, which generates and uses check data to detect errors in n-bit encoded data, allowing for simple and efficient error detection and correction with reduced circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction using ECC is implemented, then reliability of data transmission is improved, but device complexity increases due to complicated data convolution operations
Solution Approach 1:
The decoding circuit is segmented into multiple 2-bit checking units, each responsible for checking specific bit positions in the encoded data. This division allows the complex error detection task to be broken down into simpler, parallel operations, reducing overall circuit complexity while maintaining reliability
Solution Approach 2:
The invention extracts and focuses only on the essential checking operations needed for error detection, eliminating unnecessary convolution operations. By taking out only the critical 2-bit checking functions and all-bit checking function, the circuit achieves reliable error detection with minimal complexity
2Reliability
If traditional ECC methods are used for error detection and correction, then data integrity is improved, but processing speed decreases due to complex convolution operations
Solution Approach 1:
The checking process is segmented into multiple independent 2-bit checking units that can operate in parallel. This parallelization significantly increases processing speed compared to sequential convolution operations, while still ensuring data integrity through comprehensive error detection
Solution Approach 2:
The invention replaces complex mechanical convolution operations with simpler logical checking operations. By substituting the mechanical ECC process with logical AND and OR operations in the 2-bit checking units, processing speed is dramatically improved while maintaining data integrity
Data Source
AI summary
Each of (n−1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n−1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.