Decoding Circuit Module Parallel Processing for Memory Storage

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Solution Overview

Problem

Existing decoding circuits in memory storage devices are inflexible and suffer from idle time due to a sequential processing architecture, where a primary decoding circuit must wait for an advanced decoding circuit to finish before processing new data, leading to wasted system resources if the advanced circuit is consistently busy.

Innovation Solution

A decoding circuit module with a first and second decoding circuit of different decoding abilities, where data is stored in a buffer and processed independently by each circuit without waiting for the other to complete, allowing simultaneous operation and reducing idle time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a sequential decoding architecture is used where the primary decoding circuit waits for the advanced decoding circuit to finish, then the system can ensure proper error correction processing, but the primary decoding circuit experiences increased idle time and system productivity decreases

Engineering Contradiction:

Improveerror correction processingVSAvoiddecoding throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The decoding system is divided into two independent decoding circuits (first and second decoding circuits) that can operate simultaneously on different data streams. Each circuit has its own buffer and processing path, allowing parallel operation without mutual waiting, thus resolving the contradiction between reliable error correction and high productivity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system transitions from a single-dimensional sequential processing architecture to a multi-dimensional parallel architecture by introducing multiple decoding circuits operating on different data streams simultaneously. This dimensional expansion allows the system to maintain reliability through multiple processing paths while improving productivity through concurrent operations

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the primary decoding circuit continuously sends data to the advanced decoding circuit for advanced decoding, then better error correction can be achieved, but the primary decoding circuit cannot process new data when the advanced decoding circuit is busy, increasing idle time

Engineering Contradiction:

Improvedata decoding accuracyVSAvoididle time of primary decoding circuit

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system segments the decoding workload into two independent paths: a first decoding circuit for basic decoding and a second decoding circuit for advanced decoding. Each circuit operates independently with its own buffer, eliminating the waiting time that occurs when one circuit must wait for another to complete its processing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

By having multiple decoding circuits operating simultaneously and independently, the system ensures continuous useful action without idle time. When one decoding circuit is processing data, the other can simultaneously process different data streams, eliminating the idle waiting period that occurs in sequential architectures

Inventive Principle:

Principle #20Continuity of useful action

3Device complexity

If a single decoding circuit is used to process all data, then the circuit architecture is simpler, but the system cannot utilize multiple decoding circuits concurrently, reducing overall working efficiency

Engineering Contradiction:

Improvedecoding circuit architectureVSAvoiddecoding working efficiency

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The decoding system is segmented into multiple independent decoding circuits that can operate in parallel. Each circuit is relatively simple in design but the combination of multiple circuits achieves high productivity through concurrent operations, resolving the contradiction between simplicity and efficiency

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system merges multiple simple decoding circuits into a unified parallel processing architecture. Each individual circuit maintains simplicity while their combination provides enhanced productivity through simultaneous operation on multiple data streams, achieving both simplicity and high efficiency

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11599457B1Decoding circuit module, memory control circuit unit and memory storage device

Publication Date: 2023.03.07 PHISON ELECTRONICS

AI summary

A decoding circuit module, a memory control circuit unit, and a memory storage device are disclosed. The decoding circuit module is configured to decode data read from a rewritable non-volatile memory module and the decoding circuit module includes a first buffer, a second buffer, a first decoding circuit, and a second decoding circuit. The first decoding circuit is configured to decode first data read from the rewritable non-volatile memory module and stored in the first buffer. The second decoding circuit is configured to decode second data read from the rewritable non-volatile memory module and stored in the second buffer. A data decoding ability of the first decoding circuit is different from a data decoding ability of the second decoding circuit. The second data is stored in the second buffer via the first buffer and is not decoded by the first decoding circuit.