Decoding Circuit Segmentation for Display Panel Area Reduction
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Solution Overview
Problem
Existing decoding circuits for digital to analog conversion in display apparatuses face challenges in reducing size and increasing speed while maintaining precise gradation voltage generation, due to high parasitic capacitance and layout issues, especially with increasing pixel density.
Innovation Solution
A decoding circuit design that divides multibit digital data into bit groups, using sub-decoding circuits in parallel to reduce the number of elements and parasitic capacitance, allowing for high-speed operation with a smaller occupancy area by arranging unit decoders in a specific configuration to minimize vertical and horizontal sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ROM type decoding circuit using a switch matrix is used to select one electric signal from multiple candidates, then the decoding function is achieved, but the circuit occupancy area increases and parasitic capacitance increases
Solution Approach 1:
The multibit digital data is divided into multiple bit groups, and the decoding circuit is segmented into multiple bit group decoding circuits corresponding to each bit group. Each bit group decoding circuit further divides into multiple sub-decoding circuits arranged in parallel. This segmentation reduces the circuit occupancy area by distributing the decoding function across multiple smaller units rather than using a single large switch matrix.
Solution Approach 2:
The sub-decoding circuits are arranged in parallel in a direction different from the arrangement direction of the output candidates. This dimensional reorganization allows the circuit to utilize space more efficiently, reducing the occupancy area in the original arrangement direction while maintaining the decoding function.
2Reliability
If a ROM type decoding circuit using a switch matrix is used to select one electric signal from multiple candidates, then the decoding function is achieved, but the parasitic capacitance increases reducing operation speed
Solution Approach 1:
The decoding circuit is segmented into multiple sub-decoding circuits connected in parallel. Each sub-decoding circuit handles a portion of the decoding function, which reduces the parasitic capacitance compared to a single large switch matrix. Lower parasitic capacitance enables faster charging and discharging of nodes, thereby increasing the operation speed of the decoding circuit.
3Reliability
If unit decoders are arranged in a conventional configuration, then the decoding function is achieved, but the layout area increases
Solution Approach 1:
The sub-decoding circuits are arranged in parallel in a direction different from the arrangement direction of the output candidates. This dimensional reorganization optimizes the layout area by utilizing the perpendicular direction for parallel circuit placement, thereby reducing the overall footprint of the decoding circuit while maintaining full decoding functionality.
Data Source
AI summary
In each of sub-decoding circuits at a first stage provided for a plurality of output candidates arranged adjacently, for selecting corresponding output candidates in accordance with a bit of multibit data for transmission to subsequent stage sub-decoding circuits, unit decoders are arranged in parallel in a direction perpendicular to an arranging direction of the output candidates. A size in a vertical direction along which reference voltages of the output candidates of a decoding circuit are arranged can be reduced without increasing a size in a horizontal direction.