Decoding Circuit for High-Speed Snapshot Startup

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Solution Overview

Problem

Existing information processing devices face a trade-off between high-speed startup and security, as decoding snapshot images stored in non-volatile memory can slow down the startup process due to the need to decode encoded data upon power-on.

Innovation Solution

Incorporating a decoding circuit on the data bus that can switch between enabling and disabling decoding processes, allowing for high-speed decoding of snapshot images upon power-on, and an encoding circuit that can encode snapshot images before power-off, using a random number recording memory for encoding and decoding data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a snapshot image of volatile memory is encoded and stored in non-volatile memory for security, then security performance is enhanced, but decoding time increases during startup

Engineering Contradiction:

Improvesecurity performanceVSAvoiddecoding time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-loading decoding data into a dedicated decoding memory before the actual decoding process is needed. During normal operation, the system encodes snapshot images and stores them in non-volatile memory. When startup occurs, the decoding data is already prepared in the decoding memory, allowing immediate decoding without waiting for data retrieval, thus reducing decoding time while maintaining security.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a decoding memory as an intermediary component between the non-volatile storage and the processing units. This intermediary stores pre-loaded decoding data, acting as a buffer that enables fast access to decoding keys without compromising the security of the encoded snapshot images stored in non-volatile memory.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If decoding is performed using software processing, then flexibility is maintained, but startup speed decreases

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidstartup speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent replaces software-based decoding with a hardware-based decoding circuit. The decoding memory is integrated into the hardware architecture, and the decoding operations are performed by dedicated hardware logic rather than software execution. This substitution dramatically increases startup speed while maintaining the flexibility to handle different decoding scenarios through configurable hardware design.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11288374B2Information processing device, method for controlling information processing device, and program

Publication Date: 2022.03.29 MITSUBISHI HEAVY IND MACHINERY SYST LTD

AI summary

An information processing device (1) includes: a decoding circuit (12b), provided on a data bus (DB) for connecting a main memory (101) and an external storage device (11), which is capable of switching between enabling and disabling a process for decoding information that is transmitted through the data bus (DB); and a CPU (100) that is configured to read out information written in the external storage device (11) into the main memory (101). The CPU (100) is configured to enable the decoding process of the decoding circuit 12b in a case where a snapshot image of the main memory 101 is read out as the information written in the external storage device (11).