Decommissioning Microelectronic Systems via Entropy Erasure
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Solution Overview
Problem
Existing technologies fail to effectively protect hardware intellectual properties (IPs) in microelectronic systems from piracy, reverse engineering, and extraction of design secrets, especially during the deployment and end-of-life phases of electronic systems.
Innovation Solution
The implementation of Decommissioning and Erasing of Entropy in Microelectronic systems (DEEM) involves a combination of low-overhead analog and digital disabling techniques that perform irreversible transformations on critical parts of microelectronic systems, ensuring secure decommissioning and erasure of valuable secrets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware intellectual properties are stored in microelectronic systems for deployment, then the system provides functional value and service, but the system becomes vulnerable to piracy, reverse engineering, and extraction of design secrets
Solution Approach 1:
The patent implements preliminary action by pre-configuring self-destruct mechanisms and entropy erasure functions within the hardware IP during manufacturing. These mechanisms are activated before any potential theft or reverse engineering can occur, ensuring that if unauthorized access is detected or the hardware is compromised, the sensitive information is automatically destroyed in advance, preventing piracy and extraction of design secrets
Solution Approach 2:
The patent applies preliminary anti-action by incorporating countermeasures that actively prevent harmful actions before they can succeed. The system includes monitoring mechanisms that detect attempts at reverse engineering or unauthorized access, and automatically triggers entropy erasure and self-destruct functions to neutralize the threat before critical information can be extracted or stolen
2Reliability
If entropy erasure mechanisms are implemented in microelectronic systems, then security against piracy and reverse engineering is improved, but the system complexity and overhead increase
Solution Approach 1:
The patent merges the entropy erasure mechanism with existing hardware IP structures and manufacturing processes. By integrating the self-destruct functionality into the normal hardware architecture and utilizing standard manufacturing techniques, the system achieves enhanced security without proportionally increasing complexity, as the erasure mechanism shares infrastructure with existing system components
Solution Approach 2:
The patent utilizes parameter changes in the physical state of hardware components to implement entropy erasure. By changing parameters such as voltage thresholds, timing characteristics, or physical degradation states, the system can irreversibly alter hardware IP to prevent reverse engineering, achieving high security through subtle parameter modifications rather than complex structural changes
3Reliability
If irreversible transformations are performed on critical parts of microelectronic systems, then the system is protected from counterfeiting and recycling, but the ability to repair or reuse components is lost
Solution Approach 1:
The patent applies local quality by implementing irreversible transformations only in specific critical regions of the hardware IP where entropy and sensitive information are stored. The entropy erasure mechanism selectively targets particular circuits, memory regions, or logic elements while leaving other parts of the system intact, thus preventing counterfeiting and recycling of critical components while preserving the ability to repair or reuse non-critical portions
Data Source
AI summary
The present disclosure describes various embodiments of systems, apparatuses, and methods of protecting an integrated circuit. One such method comprises operating the integrated circuit under a normal mode of operation; detecting, by a decommission controller, a triggering condition for a decommission operation to be initiated for the integrated circuit; initiating, by the decommission controller, a decommission mode for the integrated circuit after detection of the triggering condition; and causing, by the decommission controller, functionality of the integrated circuit to be irreversibly disabled after initiating the decommission mode. Other methods, systems, and apparatus are also presented.