Decomposable FEC Codewords for Low-Latency Error Correction
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Solution Overview
Problem
Current network communication protocols face a trade-off between data corruption tolerance and communication latency due to the complexity and latency associated with increasing the number of parity symbols in error correction schemes, which limits flexibility in error correction power and compatibility with different communication contexts.
Innovation Solution
The implementation of decomposable forward error correction (FEC) schemes that allow for variable message lengths and variable numbers of check symbols, enabling flexible and configurable error correction power while maintaining compatibility with traditional schemes, using encoders and decoders that can efficiently produce and decode codewords in multiple FEC formats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of parity or check symbols is increased to improve error correction power, then the reliability of error correction is improved, but the complexity and latency of encoder/decoder circuitry increases
Solution Approach 1:
The patent divides a large codeword into multiple smaller sub-codewords, each processed independently by separate decoder circuits. This segmentation allows the system to achieve high error correction power for the overall message while using simpler, lower-latency decoder circuits for each sub-codeword. The parallel processing of multiple sub-codewords maintains overall reliability without requiring a single complex decoder.
2Reliability
If the number of parity or check symbols is increased to improve error correction power, then the reliability of error correction is improved, but the latency of encoder/decoder circuitry increases
Solution Approach 1:
By segmenting the codeword into smaller sub-codewords that can be decoded in parallel, the system reduces the processing time for each individual decoder circuit. The overall latency is reduced because multiple decoders work simultaneously on different sub-codewords rather than requiring a single sequential processing chain.
Solution Approach 2:
The patent applies partial action by using fewer check symbols in each sub-codeword compared to what would be needed for a single comprehensive error correction code. While each individual sub-codeword uses partial error correction capability, the combination of multiple sub-codewords achieves the desired overall error correction power with reduced per-circuit complexity and latency.
3Device complexity
If fixed codeword length schemes are used to simplify encoder/decoder design, then the device complexity is reduced, but the adaptability to different communication contexts is limited
Solution Approach 1:
The system dynamically adjusts the number of check symbols in each sub-codeword based on communication conditions. The encoder can vary the check symbol count for different sub-codewords or different transmission instances, allowing adaptation to varying channel quality requirements while maintaining a modular decoder architecture that handles variable inputs through configurable processing stages.
Data Source
AI summary
Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.