Decomposed FIR Filter Architecture for Precision and FPGA Resource Savings
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Finite impulse response (FIR) filters in digital signal processing are resource-intensive and consume significant hardware resources and power, limiting their efficiency and precision due to their large size and granularity effects from data widths of multipliers.
Innovation Solution
Decomposing FIR filters into two or more individual filters, each operating at lower input and coefficient precision, allowing for optimized bit-widths and reduced power consumption, which can improve output precision and reduce resource usage by implementing the filters in programmable logic devices like FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FIR filters are implemented with full precision multipliers to maintain output precision, then manufacturing precision is improved, but device complexity and resource usage increase significantly
Solution Approach 1:
The patent divides a single high-precision FIR filter into multiple lower-precision sub-filters. Each sub-filter processes a portion of the input signal with reduced bit-width multipliers, and their outputs are combined to achieve the desired overall precision. This segmentation reduces the complexity of individual multiplier operations while maintaining the cumulative precision through parallel processing of multiple sub-filters.
2Manufacturing precision
If FIR filters use higher data width multipliers to improve output precision, then manufacturing precision is improved, but the area of the integrated circuit increases
Solution Approach 1:
The patent segments the high-precision filtering function into multiple lower-precision sub-filters. By using several multipliers with smaller bit-widths (e.g., 16×16 or 18×18) instead of one or fewer high-bit-width multipliers, the overall die area is reduced. The combined output of these smaller multipliers achieves the required precision while occupying less silicon real estate than equivalent high-precision multipliers would require.
3Device complexity
If FIR filters are implemented with reduced precision multipliers to reduce resource usage, then device complexity is reduced, but output precision deteriorates
Solution Approach 1:
The patent combines the outputs of multiple lower-precision sub-filters to achieve the precision of a single high-precision filter. Each sub-filter uses simplified multipliers with reduced bit-widths, but their combined results through addition and proper scaling restore the overall output precision. This merging approach allows the system to benefit from reduced complexity in individual components while achieving high precision in the aggregate output.
4Reliability
If FIR filters use more taps to improve filtering performance, then reliability is improved, but the number of multipliers and resource usage increase
Solution Approach 1:
The patent segments the filter into multiple sub-filters, each handling a portion of the taps. By distributing the tap processing across several sub-filters with reduced-precision multipliers, the total number of high-resource multipliers is reduced. The segmentation allows parallel processing of tap contributions while using more economical multiplier units, thereby maintaining filtering performance with fewer overall multipliers.
Data Source
AI summary
Circuitry, systems, and methods are provided for an integrated circuit that includes digital filter circuitry. The digital filtering circuitry includes a first partial filter that includes a first number of taps corresponding to coefficients of a first bit depth and a second partial filter that includes a second number of taps corresponding to coefficients of a second bit depth.