Decompressor Self-Loop States for Low Power Scan Chain Testing
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Solution Overview
Problem
Existing test pattern generation methods for integrated circuits result in high power consumption during testing due to excessive switching in scan chains, leading to potential device malfunction or reliability degradation.
Innovation Solution
The proposed method generates test patterns that reduce switching rates and power dissipation in scan chains by using self-loop states in decompressors, which are assigned to specific scan chain shift cycles, allowing for reproducible output values and minimizing transitions, without requiring hardware modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test pattern generation methods are used, then test coverage is achieved, but power consumption during testing increases due to excessive switching in scan chains
Solution Approach 1:
The patent changes the parameters of the decompressor operation by introducing self-loop states that maintain constant output values across multiple clock cycles. This parameter change in the decompressor's state transition behavior reduces switching activity in scan chains while maintaining test coverage, directly addressing the power consumption issue.
Solution Approach 2:
The patent implements periodic self-loop states in the decompressor where the output remains constant for multiple clock cycles. This periodic action pattern allows the scan chains to receive repeated identical patterns, reducing switching activity and power consumption while still achieving comprehensive fault coverage through systematic pattern application.
2Productivity
If compressed test patterns are used to reduce test data volume, then data transmission efficiency improves, but switching rates and power dissipation increase due to random determination of unspecified bits
Solution Approach 1:
The patent changes the parameter of bit determination from random to deterministic by using self-loop states. This parameter change ensures that unspecified bits are determined systematically rather than randomly, reducing switching activity while maintaining high compression ratios and improving power efficiency.
Solution Approach 2:
The patent implements feedback mechanisms where the decompressor's self-loop states are designed to produce consistent output patterns that minimize switching. The feedback in the state transition logic ensures that once a self-loop state is entered, the output remains stable, reducing power dissipation while maintaining compression effectiveness.
3Productivity
If high compression ratios are achieved through deterministic test patterns, then test data volume is reduced, but test time increases due to solving linear equations
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the solutions to linear equations that define the self-loop states. This preliminary computation is performed offline during test pattern generation, so that during actual testing, the pre-computed patterns can be applied directly without real-time computation, thus achieving high compression ratios without increasing test time.
Data Source
AI summary
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.