Hardware Deconvolution Circuit for Image Blur Reduction

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Solution Overview

Problem

Digital imaging systems, particularly low-cost and small-size cameras, often produce images that are blurred or distorted due to non-negligible optical point spread functions (PSFs), which existing methods struggle to effectively compensate for.

Innovation Solution

An image enhancement circuit with a two-dimensional array of filter cells applying deconvolution kernels to separate and filter interleaved pixel values from mosaic image sensors, reducing blur by multiplying input pixel values with deconvolution coefficients that approximate the inverse of the PSF, and accumulating results to produce deblurred sub-images.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If digital image processing is used to compensate for non-ideal PSFs, then image quality can be improved, but processing complexity and computational resources increase

Engineering Contradiction:
Improveimage qualityVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the deconvolution operation into multiple scanning passes over the image data. Each pass processes a portion of the convolution sum, allowing the complex computation to be broken into manageable segments that can be executed sequentially with minimal memory requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic scanning of image lines through multiple passes, where each pass processes the image data in a systematic sequence. This periodic action allows the processing to be distributed over time while maintaining the integrity of the deconvolution operation.

Inventive Principle:
Principle #19Periodic action

2Productivity

If hardware-based deconvolution is implemented, then processing speed can be improved, but device complexity and resource requirements increase

Engineering Contradiction:
Improveprocessing speedVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple processing functions into a single hardware circuit that performs deconvolution operations. The circuit integrates pixel value storage, coefficient multiplication, accumulation, and output generation in one unified structure, reducing overall hardware complexity while maintaining processing speed.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hardware circuit is designed to automatically perform the deconvolution operation by internally managing the multiplication and accumulation of pixel values with coefficients. The circuit serves itself by maintaining internal state registers and automatically progressing through the computation without external intervention for each step.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If deconvolution filtering is applied to reduce blur, then image clarity can be improved, but loss of information and noise amplification occur

Engineering Contradiction:
Improveimage clarityVSAvoidinformation loss
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent allows dynamic adjustment of the point spread function parameters that define the blur characteristics. By changing these parameters based on the specific imaging conditions, the deconvolution process can be optimized to recover image details while minimizing noise amplification and information loss.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8154636B2Image enhancement using hardware-based deconvolution
Publication Date: 2012.04.10 DIGITALPTICS CORP INT
  • US8154636B2 patent drawing
  • US8154636B2 patent drawing
  • US8154636B2 patent drawing

AI summary

An image enhancement circuit (26, 60, 190, 260) includes an input interface (64, 262), which is operative to accept a stream of input pixel values belonging to pixels (32) of an input image. The input image includes a plurality of different input sub-images including respective subsets of the pixels, such that the input pixel values of the pixels in the different input sub-images are interleaved in the stream. A plurality of filter cells (92, 144, 206, 222, 238, 364) are connected in a two-dimensional array configuration and are arranged to separately filter the input pixel values of each of the input sub-images with respective two-dimensional deconvolution kernels so as produce respective output sub-images that include output pixel values. A multiplexer (88, 332) is coupled to multiplex together the output pixel values of the output sub-images so as to produce a filtered output image.