Decoupled Access-Execute Circuitry Prefetch Control

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Solution Overview

Problem

Current data processing systems face inefficiencies due to the limitations of decoupled access-execute processing and prefetching techniques, which can be complementary but often require independent control, leading to suboptimal performance under changing conditions.

Innovation Solution

The integration of decoupled access-execute processing circuitry with prefetch circuitry, where the control of the access portion and prefetch circuitry is dependent on performance metrics of each other, allowing for adaptive operation to optimize data retrieval and cache management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If decoupled access-execute processing is implemented to run access phase ahead of execute phase, then data supply to execution units is improved and cache misses are reduced, but device complexity increases due to separate access and execute portions

Engineering Contradiction:
Improveinstruction throughputVSAvoidprocessor architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor is divided into separate access portion and execute portion, with the access portion handling load-related instructions and the execute portion handling data processing instructions. This segmentation allows independent optimization of each portion and enables the access phase to run ahead of the execute phase, improving data supply to execution units.

Inventive Principle:
Principle #1Segmentation

2Productivity

If prefetch circuitry is used to proactively access predicted memory addresses, then cache hits are increased and instruction execution is improved, but energy consumption increases due to additional memory access operations

Engineering Contradiction:
Improveinstruction execution efficiencyVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system uses feedback from performance metrics (cache hit rate, stall cycles, memory bandwidth utilization) to dynamically control prefetch circuitry operation. When metrics indicate sufficient cache performance, prefetching is reduced or disabled; when metrics show cache misses or execution stalls, prefetching is activated or intensified, optimizing the balance between performance and energy consumption.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The prefetch circuitry operation is made dynamic through adaptive control based on real-time performance monitoring. The system adjusts prefetching aggressiveness, enabled/disabled states, and target cache levels dynamically in response to changing workload characteristics and cache performance, rather than operating in a fixed mode.

Inventive Principle:
Principle #15Dynamics

3Ease of manufacture

If independent control of access portion and prefetch circuitry is used, then each component can be optimized separately, but overall system performance becomes suboptimal under changing conditions

Engineering Contradiction:
Improvecomponent optimizationVSAvoidsystem adaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The control circuitry is designed to universally manage both the access portion and prefetch circuitry through common performance metrics and coordinated control signals. This multi-functional control approach allows the same control logic to adaptively regulate both components based on overall system performance, enabling them to work together synergistically rather than in isolation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11886881B2Decoupled access-execute processing and prefetching control
Publication Date: 2024.01.30 ARM LTD
  • US11886881B2 patent drawing
  • US11886881B2 patent drawing
  • US11886881B2 patent drawing

AI summary

Apparatuses and methods are provided, relating to the control of data processing in devices which comprise both decoupled access-execute processing circuitry and prefetch circuitry. Control of the access portion of the decoupled access-execute processing circuitry may be dependent on a performance metric of the prefetch circuitry. Alternatively or in addition, control of the prefetch circuitry may be dependent on a performance metric of the access portion.