Decoupled Access-Execute Processor Steering Instructions
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Solution Overview
Problem
Conventional processors face delays due to cache misses and memory access issues, which hinder instruction execution progress by stalling execute instructions when access instructions encounter memory latency.
Innovation Solution
A decoupled access-execute processor architecture, where instructions are categorized as 'access' or 'execute' using a novel 'steering instruction' that directs subsequent instructions to appropriate execution paths, prioritizing access instructions and deferring execute instructions to overlap memory access with computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are executed in a conventional sequential manner, then instruction execution simplicity is maintained, but processor efficiency deteriorates due to stalls caused by memory access latency
Solution Approach 1:
The processor is divided into two separate execution paths: an access execution path for handling memory access instructions and an execute execution path for handling computation instructions. This segmentation allows independent optimization of each path and enables parallel processing, thereby improving processor efficiency without requiring a complete architectural overhaul
Solution Approach 2:
The system performs preliminary classification of instructions into access and execute categories using steering instructions. By determining the execution path in advance through decode circuitry that detects predetermined instruction types, the processor can prepare and issue instructions to the appropriate execution path before actual execution begins, reducing stalls and improving overall efficiency
2Loss of time
If access instructions are prioritized over execute instructions, then memory access latency impact is reduced, but instruction execution control complexity increases
Solution Approach 1:
The decode circuitry performs preliminary identification of access instructions by detecting predetermined instruction types in the instruction stream. This early detection allows the issue circuitry to prioritize access instructions for issuance to the access execution path before execute instructions, ensuring that memory access operations are initiated as early as possible without requiring complex runtime arbitration mechanisms
Solution Approach 2:
The issue circuitry acts as an intermediary between the decode circuitry and the dual execution paths. It receives decoded instructions and uses control signals generated by decode circuitry to direct instructions to either the access execution path or execute execution path, thereby managing the prioritization logic in a centralized manner that simplifies overall control complexity
3Productivity
If instructions are decoupled into separate access and execute paths, then overlap between memory access and computation is improved, but instruction decoding complexity increases
Solution Approach 1:
The decode circuitry is enhanced with localized detection capability for predetermined instruction types that indicate access operations. Rather than implementing a complete analysis of all instruction characteristics, the system applies a targeted decoding approach that identifies access instructions through specific type detection, enabling effective separation of execution paths with minimal additional decoding complexity
Data Source
AI summary
Data processing apparatuses, methods of data processing, instructions, and simulator computer programs for providing a corresponding instruction execution environment are disclosed. Decode circuitry is responsive to an instance of a predetermined instruction type to cause issue circuitry to issue at least one subsequent instruction for execution to one of first and second instruction execution circuitry which support decoupled access-execute instruction execution. The predetermined instruction type is thus a steering instruction for at least one subsequent instruction and the programmer is provided with a mechanism for determining which program instructions are treated as access instructions and which are treated as execute instructions.