Decoupled Cache Memory for Concurrent Video Data Processing
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Solution Overview
Problem
Existing video-data processing devices are limited by their inability to perform reading and fetching operations concurrently, which restricts processing speed and efficiency due to the sequential nature of cache memory operations.
Innovation Solution
A data processing device with a high-level cache unit and a low-level cache unit that allows concurrent reading and fetching operations by decoupling fetching and reading functionalities, where the high-level cache handles fetching parameters and the low-level cache handles reading parameters, enabling parallel communication and computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single cache memory unit is used for both reading and fetching operations, then the device complexity is reduced, but the processing speed decreases due to sequential operations
Solution Approach 1:
The cache memory is segmented into two independent functional units: a first cache memory unit dedicated to reading operations and a second cache memory unit dedicated to fetching operations. This segmentation allows both operations to execute simultaneously without interfering with each other, thereby resolving the contradiction between simplified structure and high processing speed.
2Device complexity
If reading and fetching operations are performed sequentially in a single cache unit, then the device structure remains simple, but the latency increases
Solution Approach 1:
By dividing the cache into separate reading and fetching units, the patent eliminates the sequential execution bottleneck. The reading unit can service read requests while the fetching unit simultaneously pre-fetches data, thereby reducing overall latency without significantly increasing structural complexity.
Solution Approach 2:
The fetching cache memory unit performs preliminary data fetching in advance, preparing data before it is needed by the processing unit. This preliminary action reduces the time penalty associated with cache misses and data retrieval latency.
3Productivity
If a single cache unit handles both reading and fetching, then the bandwidth is limited by sequential access, but adding separate units increases device complexity
Solution Approach 1:
The cache memory is divided into two independent units with separate data buses and control logic. This segmentation enables parallel data flow paths, effectively doubling the data throughput compared to a single sequential cache unit, while keeping each individual unit relatively simple in structure.
Solution Approach 2:
Each cache memory unit is designed with universal functionality to handle its designated operation type (reading or fetching) for various data types and access patterns. This multi-functionality within each unit allows the system to achieve high productivity across different workloads without requiring specialized structures.
Data Source
AI summary
The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (14). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.