Decoupled Gate Stress-Test Circuit for Power Transistor Pads
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Solution Overview
Problem
Existing power electronic circuits face challenges in stress testing power transistors without damaging control circuits and cannot simultaneously test high-side and low-side transistors due to shared contact pads, necessitating additional protection components and dedicated pads for measurement.
Innovation Solution
The power electronic circuit design decouples contact pads during stress testing to apply different electrical potentials to power transistors and control circuits, allowing simultaneous testing of high-side and low-side transistors without subjecting control circuits to high stress voltages, and integrates encapsulation to couple pads post-testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress voltage is applied to test power transistors, then transistor defects can be identified, but control circuits may be damaged by the high voltage
Solution Approach 1:
The contact pads are segmented into two separate pads: a first contact pad for applying stress voltage to the power transistor, and a second contact pad for the control circuit. This physical separation allows independent voltage application, enabling stress testing without damaging the control circuit.
Solution Approach 2:
The patent uses an intermediary structure (separate contact pads) to mediate between the stress voltage source and the power transistor, preventing direct exposure of the control circuit to harmful high voltage while still enabling effective stress testing of the transistor.
2Device complexity
If shared contact pads are used for high-side and low-side transistors, then circuit structure is simplified, but simultaneous testing of both transistors is prevented
Solution Approach 1:
The contact pad structure is segmented into multiple independent pads (first and second contact pads for high-side, third and fourth contact pads for low-side transistors), enabling parallel stress testing of both high-side and low-side transistors simultaneously without interference.
Solution Approach 2:
The patent transitions from a single-shared contact pad approach to a multi-pad dimensional structure, allowing simultaneous application of different stress voltages to different transistor groups, thereby increasing testing throughput and productivity.
3Object-affected harmful factors
If additional protection components are added to protect control circuits, then control circuits are protected from stress voltage, but device complexity increases
Solution Approach 1:
The protection mechanism is extracted from the circuit interior to the contact pad level. By separating the contact pads, the control circuit is inherently protected from stress voltage without requiring additional protection components within the circuit, thus reducing overall device complexity.
4Measurement precision
If dedicated internal contact pads are used for stress testing, then leakage current measurement is enabled, but the number of contact pads increases
Solution Approach 1:
The first and second contact pads serve multiple functions: they are used for stress voltage application during testing, for leakage current measurement, and after encapsulation, they become interconnected to form part of the operational circuit. This multi-functionality reduces the need for additional dedicated pads.
Data Source
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AI summary
The present description relates to a power electronic circuit (100) comprising at least one power transistor (102, 106) whose gate is coupled to a control circuit (104, 108) and whose source is coupled to a first contact pad (114, 124), in which the control circuit (104, 108) is coupled to a second contact pad (116, 126), and in which the first and second contact pads (114, 116, 124, 126) are configured to be decoupled from each other when the power electronic circuit (100) is in a stress test configuration of the gate of the power transistor (102, 106) and configured to be coupled to each other when the power transistor (102, 106) and the control circuit (104, 108) are encapsulated.