Decoupled Interconnect Structure for Low-Damage Pillar and Via Formation
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Solution Overview
Problem
In semiconductor device fabrication, existing methods face challenges such as dielectric and metal damage, seams, and voids in interconnects, particularly during the formation of pillars and vias, leading to reliability issues and high resistive-capacitive delays.
Innovation Solution
The approach involves forming lower-level interconnect structures after associated devices or pillars, allowing for decoupled interconnects and preventing damage to dielectrics during patterning, using a subtractive scheme where a metal layer is deposited and selectively etched to form lines and vias, with an insulative layer covering the initial interconnect structure to protect it from subsequent fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pillars and vias are formed during conventional interconnect fabrication, then electrical connection between layers is achieved, but dielectric damage and seams/voids occur leading to reliability issues
Solution Approach 1:
The patent divides the interconnect formation process into separate stages: first forming lower-level interconnect structures (metal layers 1-3), then forming pillars, and finally forming upper-level interconnect structures (metal layers 4-6). This segmentation allows each stage to be optimized independently, preventing dielectric damage that would occur if all structures were formed simultaneously in conventional processes.
Solution Approach 2:
The patent performs preliminary formation of lower-level interconnect structures and applies an insulative layer capping before forming pillars. This preliminary action protects the already-formed interconnects from damage during subsequent pillar formation processes, eliminating the need for harmful etch-back steps that cause dielectric damage and voids.
2Reliability
If conventional interconnect formation methods are used, then interconnects are formed, but high resistive-capacitive delays occur
Solution Approach 1:
The patent introduces vertical dimensionality by forming pillars that extend through the insulative layer, enabling three-dimensional integration of interconnect structures. This allows signals to travel through shorter horizontal paths while maintaining electrical connectivity, reducing resistive-capacitive delays associated with planar interconnect layouts.
3Ease of manufacture
If interconnects are formed at the same level, then fabrication is simplified, but device flexibility for various sizes and configurations is limited
Solution Approach 1:
The patent creates a dynamic, multi-level interconnect architecture where lower-level interconnects, pillars, and upper-level interconnects can be independently configured. This dynamic structure allows the same fabrication platform to support various device sizes and configurations by adjusting the placement and connectivity of interconnect elements at different vertical levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves device reliability by preventing dielectric damage and reducing resistive-capacitive delays, enabling the formation of interconnects at different depths and facilitating various device sizes and configurations.
Implementation Method 1
using a subtractive scheme where a metal layer is deposited and selectively etched to form lines and vias
Implementation Method 2
with an insulative layer covering the initial interconnect structure to protect it from subsequent fabrication processes
Data Source
AI summary
A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.