Decoupled Interconnect Formation for Semiconductor Reliability
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Solution Overview
Problem
As integrated circuits move to smaller technology nodes, the simultaneous patterning of interconnects and devices becomes increasingly challenging due to issues like seams and voids in dielectric fill, dielectric and metal damage causing high resistive-capacitive (RC) delays, and metal sidewall damage, which affect device reliability and interconnect manufacturability.
Innovation Solution
The method involves forming a first bottom interconnect in a device area, fabricating a device on top, capping it with a dielectric, exposing a logic area by removing a portion of the dielectric, and forming a second bottom interconnect in the logic area, allowing for separate patterning and reducing damage to the device and interconnects, thereby improving reliability and reducing RC delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simultaneous patterning of interconnects and devices is performed, then fabrication process is simplified, but damage to dielectric and metal occurs causing high RC delays
Solution Approach 1:
The fabrication process is divided into separate stages: device formation in the device area is completed first, then interconnect patterning is performed in the logic area after device capping. This segmentation prevents simultaneous patterning conflicts and avoids damage to dielectric and metal layers, thereby maintaining device reliability while still achieving manufacturing efficiency.
Solution Approach 2:
The device area is prepared and capped with dielectric material before interconnect patterning begins in the logic area. This preliminary action protects the device structure from damage during subsequent interconnect fabrication steps, preventing metal sidewall damage and dielectric cap damage that would cause high RC delays.
2Reliability
If decoupled interconnect formation is implemented, then damage to device and interconnects is reduced, but fabrication process complexity increases
Solution Approach 1:
Different fabrication approaches are applied to different areas of the substrate: the device area receives protective capping dielectric to prevent damage during interconnect formation, while the logic area undergoes standard interconnect patterning. This local differentiation protects critical device structures without unnecessarily complicating the overall fabrication process.
3Quantity of substance
If more interconnect layers are added to support increased memory devices, then device capacity increases, but chip size increases proportionally
Solution Approach 1:
Instead of expanding chip area horizontally to accommodate more interconnect layers, the invention utilizes vertical stacking of interconnect layers above the logic area. This three-dimensional interconnect architecture allows multiple memory devices to be supported by stacking interconnect layers vertically, thereby increasing device capacity without proportionally increasing chip size.
Data Source
AI summary
A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.