Decoupled Lookup Table Accelerator for Faster SoC Table Access
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Solution Overview
Problem
Conventional vector processing units (VPUs) face inefficiencies in handling dynamic range detection, memory bank utilization, data manipulation, and programming complexity, leading to increased latency and processing overhead, particularly in safety-critical applications like autonomous vehicles.
Innovation Solution
Implementing a min/max hardware collector, automatic predication, and decoupled accelerators within the VPU architecture to reduce latency, optimize memory access, and streamline DMA operations, along with a hardware sequencer for frame-level sequencing to minimize intervention from processing controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If table lookup operations are performed using conventional VPUs with replicated tables or additional read ports, then lookup speed may be improved, but memory usage and chip space requirements increase
Solution Approach 1:
The patent divides the lookup table into multiple segments stored in different memory banks, allowing parallel access to different segments. Instead of replicating the entire table across multiple banks, each bank holds a portion of the table data. The system uses segmented addressing to direct queries to the appropriate memory bank segment, reducing total memory requirements while maintaining parallel lookup capability.
Solution Approach 2:
The patent introduces a new dimension of organization by dividing the lookup table across multiple memory banks with segmented addressing. This transforms the traditional single-table replication approach into a multi-dimensional storage structure where data is distributed across banks and accessed through segmented addresses, enabling parallel access without full replication.
2Productivity
If software pipelining and loop unrolling are used to achieve high throughput, then processing speed improves, but code size and latency increase due to remainder loops
Solution Approach 1:
The patent implements automatic iteration management where the hardware automatically handles the iteration count and determines when to terminate loop operations. The VPU autonomously manages the number of iterations without requiring complex software control structures, eliminating the need for remainder loops and associated conditional logic while maintaining high throughput processing.
3Ease of operation
If standard memory read operations are used with consistent unit requirements, then memory access simplicity is maintained, but efficiency decreases when reading partial vector widths
Solution Approach 1:
The patent enables different memory read widths for different lanes within the same vector processing unit. Each lane can independently specify its required data width, allowing efficient reading of partial vector widths without requiring standardization across all lanes. This local customization of read width optimizes memory efficiency while maintaining operational simplicity through lane-level independence.
4Device complexity
If data is stored in local data memory without data caches, then programming complexity is reduced, but access latency increases for repeated data
Solution Approach 1:
The patent implements data caches that pre-load and store frequently accessed data before it is needed for processing. The cache system proactively retrieves data in advance based on predicted access patterns, eliminating wait time during data access operations. This preliminary data preparation reduces access latency without significantly increasing programming complexity, as the cache management is handled autonomously by the hardware.
Data Source
AI summary
In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.