Decoupled Memory Cell Program Erase Channels
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Solution Overview
Problem
Non-volatile memory (NVM) circuits face challenges in endurance and data retention due to program-induced and erase-induced degradation, which affects their performance and reliability, especially at extreme temperatures.
Innovation Solution
The memory cell design decouples program and erase channels by using an access transistor and a storage transistor coupled in series, with a program gate and an erase gate, allowing for separate operations and reducing degradation effects on the read channel, thereby enhancing endurance and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If program and erase operations share common channels in conventional NVM cells, then device complexity is reduced, but program-induced and erase-induced degradation affect endurance and data retention
Solution Approach 1:
The memory cell is segmented into distinct program and erase channels with separate transistor pathways. The program channel uses access transistor AT and storage transistor ST with program gate PG, while the erase channel uses access transistor AT and storage transistor ST with erase gate EG. This segmentation allows independent operation of program and erase functions, preventing degradation from one operation from affecting the other channel, thereby improving endurance and data retention.
2Reliability
If separate program and erase channels are implemented, then program-induced and erase-induced degradation are decoupled improving reliability, but device complexity increases
Solution Approach 1:
The memory cell implements segmented program and erase channels where program operations flow through access transistor AT and storage transistor ST controlled by program gate PG, while erase operations flow through access transistor AT and storage transistor ST controlled by erase gate EG. This segmentation physically separates the degradation pathways, allowing the cell to endure more programming and erasing cycles without cumulative damage.
Solution Approach 2:
The access transistor AT and storage transistor ST serve as intermediaries that can be selectively activated for either program or erase operations. By using the same transistors as intermediaries for both channels but controlling them through different gates (PG for program, EG for erase), the design achieves channel separation while maintaining structural efficiency.
3Ease of manufacture
If conventional NVM cells are used without decoupled channels, then manufacturing is simpler, but soft erases and mobility degradation occur reducing performance
Solution Approach 1:
The memory cell structure is segmented into distinct program and erase operational pathways using separate gate controls (PG and EG). During fabrication, this segmentation is implemented by forming separate gate structures over the common transistor channels, allowing standard manufacturing processes to produce the decoupled channels without requiring fundamentally new fabrication techniques.
Solution Approach 2:
The access transistor AT and storage transistor ST serve universal functions for both program and erase operations. These transistors can be activated through different gates depending on the desired operation, making them multi-functional components that reduce the need for additional dedicated structures while maintaining channel separation benefits.
Data Source
AI summary
A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.