Decoupled MLC Memory Row Buffer for Latency and Energy Reduction
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Solution Overview
Problem
Multi-level cell (MLC) technology in non-volatile memories like Phase Change Memory (PCM) incurs higher access latency and energy due to the need for precise resistance control, leading to iterative writing and reading techniques that increase read and write latency and energy consumption.
Innovation Solution
Decoupling Most-Significant Bits (MSBs) and Least-Significant Bits (LSBs) in memory cells, storing them in separate buffer portions of a row buffer, and interleaving data blocks to take advantage of read and write asymmetries, allowing for reduced latency and energy in memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC technology is used to increase memory density, then storage capacity increases, but access latency and energy consumption increase due to precise resistance control requirements
Solution Approach 1:
The patent segments the MLC memory cell into two independent SLC portions: an MSB portion storing most-significant bits and an LSB portion storing least-significant bits. Each portion can be accessed independently, allowing the system to read MSBs quickly without waiting for LSB programming to complete, thereby reducing access latency while maintaining high memory density through MLC architecture
2Manufacturing precision
If iterative writing techniques are used to achieve precise resistance control, then manufacturing precision improves, but energy consumption increases
Solution Approach 1:
By dividing the MLC cell into separate MSB and LSB portions, each with its own independent programming circuitry, the system can program each portion separately with optimized pulse sequences. This reduces the total energy required compared to traditional iterative approaches that must repeatedly program the entire cell to achieve precise resistance control for multiple bits
3Measurement precision
If multiple sensing iterations are used to read MLC cells, then measurement precision improves, but read latency and energy consumption increase
Solution Approach 1:
The patent enables independent sensing of MSB and LSB portions through separate sensing circuits. The MSB portion can be sensed immediately after selection without waiting for LSB read operations, allowing parallel sensing that maintains high measurement precision while significantly reducing read latency compared to sequential sensing of all bits in an MLC cell
4Quantity of substance
If MLC technology is implemented, then memory capacity increases, but device complexity increases due to iterative writing and reading techniques
Solution Approach 1:
The patent divides the MLC memory into independent MSB and LSB portions with separate control logic, sensing circuits, and programming pathways. This segmentation simplifies the control complexity by allowing independent management of each portion, eliminating the need for complex iterative coordination required in traditional MLC operations, while still achieving high memory capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves memory latency and energy efficiency by allowing MSBs to be read at lower latency and energy, and LSBs to be written at lower latency and energy, while mitigating endurance overhead through coalesced writes, resulting in improved system performance and energy efficiency.
Implementation Method 1
PCM is an emerging memory technology that stores data by varying the electrical resistance of a material known as chalcogenide. By applying heat, and then allowing it to cool at different rates, chalcogenide can be manipulated to settle between an amorphous (quickly quenched) high resistance state (e.g., a logic low or zero) and a crystalline (slowly cooled) low resistance state (e.g., a logic high or one).
Implementation Method 2
By applying heat, and then allowing it to cool at different rates, chalcogenide can be manipulated to settle between an amorphous (quickly quenched) high resistance state and a crystalline (slowly cooled) low resistance state
Data Source
AI summary
A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.