Decoupled Packet and Cell Queueing for Scalable Output Queues

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Solution Overview

Problem

Conventional network switches face challenges in handling multiple unique flows simultaneously due to thresholding operations and linked-list based queueing structures, leading to inefficiencies in data rate handling and increased latency at high bandwidths.

Innovation Solution

A scalable output queued architecture with decoupled packet and cell queueing, where packet and cell control operations are handled independently, using separate pointers and storage for efficient admission control and queue management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional linked-list based queueing structure is used, then packet storage and control can be implemented, but system complexity increases and performance degrades at high bandwidth

Engineering Contradiction:
ImprovethroughputVSAvoidqueueing structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the queueing structure into separate packet queues and cell queues, eliminating the need for complex linked-list based structures. Packet queues store packet headers while cell queues store actual payload data, allowing independent management and simplifying the overall system architecture while maintaining high throughput performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts cell control information from the packet control path and places it in separate cell queues. This extraction removes the complexity of traversing linked lists at high rates and reduces the number of reads/writes to shared storage, directly improving throughput without increasing device complexity

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If shared storage is used for control information, then memory usage is reduced, but number of reads/writes increases causing performance degradation

Engineering Contradiction:
Improvedata rate handlingVSAvoidstorage access overhead
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent segments storage into separate packet storage and cell storage structures. Packet control information is stored in packet queues while cell control information is stored in cell queues, reducing the frequency of reads/writes to shared storage and improving data rate handling performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces separate queue structures as intermediaries between the packet processing units and the shared storage. These queues act as buffers that reduce the number of direct accesses to shared memory, thereby reducing storage access overhead and improving overall data rate handling

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If thresholding operations are performed for multiple unique flows, then packet admission control is achieved, but processing time increases leading to higher latency

Engineering Contradiction:
Improveadmission controlVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments admission control into separate packet admission control and cell admission control processes. Packet admission control determines whether to admit packets to packet queues, while cell admission control handles cell-level thresholding, reducing the processing time for each operation and lowering overall latency while maintaining reliable admission control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs packet admission control decisions before cell-level processing. By making admission decisions at the packet level first and only performing cell-level thresholding for admitted packets, the system reduces processing time and latency while ensuring reliable admission control through preliminary action

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260039606A1Scalable Output Queued Architecture with Decoupled Packet and Cell Queueing
Publication Date: 2026.02.05 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20260039606A1 patent drawing
  • US20260039606A1 patent drawing
  • US20260039606A1 patent drawing

AI summary

A network device with decoupled packet and cell queueing is provided. The network device includes a traffic manager configured to obtain the one or more packets. The traffic manager further includes a packet storage configured to store one or more pointers associated with a packet of the one or more packets, the one or more pointers comprising a first type of pointer and a second type of pointer, and a cell storage configured to store cell control information of at least part of the one or more cells of the packet, wherein the cell control information includes a respective first type of pointer for each of the at least part of the one or more cells. The traffic manager further includes admission control logic configured to perform an admission check of the one or more packets without the cell control information of the one or more packets.